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Texas Instruments PGA116AIPW
- Part No.:
- PGA116AIPW
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
PGA116AIPW.pdf
- Description:
- IC OPAMP PGA 1 CIRCUIT 20TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,978
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Product details
Overview
PGA116AIPW from Texas Instruments is a zero-drift programmable gain amplifier with 10-channel analog multiplexer, binary gain selection (1–128×), SPI interface, and internal calibration channels. It delivers 25 μV typical offset, 0.35 μV/°C drift, 12 nV/√Hz noise, rail-to-rail output swing, and operates from 2.2 V to 5.5 V supplies - used in precision sensor signal conditioning for industrial metering and portable data acquisition.
For engineers reviewing the PGA116AIPW datasheet, PGA116AIPW pinout, PGA116AIPW application, or PGA116AIPW equivalent, key selection criteria include its 10-input MUX capability, daisy-chain SPI support, hardware/software shutdown (≤4 μA), AVDD/DVDD dual-supply isolation, and calibration channel integration for system-level offset/gain correction in battery-powered and high-accuracy measurement systems.
Technical Context
The PGA116AIPW integrates a zero-drift chopper-stabilized amplifier core with a 10-channel analog multiplexer and SPI-controlled gain switching (200 ns). Its dual supply architecture (AVDD for analog path, DVDD for digital I/O and output stage) prevents ADC overvoltage when interfacing with lower-voltage microcontrollers like MSP430.
Four internal calibration channels (GND, 0.1VCAL, 0.9VCAL, VREF) enable end-system self-calibration without external components. Gain programming uses binary steps (1, 2, 4, ..., 128) and supports both software (SPI register write) and hardware (ENABLE pin) shutdown modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | Binary gains: 1× to 128× - enables precise scaling of low-level sensor outputs before ADC sampling. |
| Input Offset Voltage | ±25 μV typical (±100 μV max) - ensures <0.1% error at 25 mV input with G=1, critical for strain gauge or thermocouple front-ends. |
| Offset Drift | 0.35 μV/°C typical - maintains accuracy across –40°C to 125°C industrial temperature range without recalibration. |
| Input Voltage Noise | 12 nV/√Hz @ >10 kHz - preserves SNR in dynamic signal acquisition up to ~100 kHz bandwidth. |
| Supply Range | AVDD/DVDD = 2.2 V to 5.5 V - supports mixed-voltage systems (e.g., 3.3 V MCU + 5 V analog rail). |
| Quiescent Current | 1.1 mA typical total (0.45 mA analog + 0.75 mA digital @ 10 MHz SCLK) - enables multi-day battery life in handheld instruments. |
| Shutdown Current | ≤4 μA - reduces power during idle periods in energy-constrained remote monitoring nodes. |
| SPI Interface | 10 MHz max clock, daisy-chain capable - allows compact control of multiple PGAs using single MCU SPI port. |
Pinout & Package
TSSOP-20 package (6.50 mm × 4.40 mm), thermally enhanced for industrial ambient operation; pin-compatible with PGA117 but configured for binary gain mode.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 AVDD | Analog supply input | Power source for amplifier core and mux; must be bypassed with 0.1 μF ceramic capacitor near pin. |
| 7 VCAL/CH0 | Multiplexer channel 0 / calibration reference input | Connects to external low-impedance VCAL voltage; selects internal calibration channels (GND, 0.1VCAL, 0.9VCAL, VREF) via SPI. |
| 8 VREF | Reference input | Sets output common-mode level; must drive ≥2 mA sink/source or tie to GND for midsupply referenced output. |
| 9 VOUT | Analog output | Rail-to-rail output stage; clamped to AVDD + 300 mV if AVDD < DVDD - protects downstream 3 V ADC inputs. |
| 13 ENABLE | Hardware shutdown control | Logic low forces shutdown (IQ ≤1 μA); complements SPI software shutdown for fail-safe power management. |
| 15 SCLK | SPI clock input | Accepts up to 10 MHz clock; timing-critical for gain/channel switching latency (200 ns). |
| 16 DIN | SPI data input | Weak 10 μA pulldown enables daisy-chain connection without external pull-down resistors. |
| 17 DOUT | SPI data output | High-impedance when CS high - allows multiple devices on shared SPI bus. |
| 18 CS | SPI chip select | Active-low enable for SPI communication; controls DOUT high-Z state and command latching. |
| 19 DVDD | Digital/output stage supply | Defines logic levels and powers op-amp output stage; isolates digital noise from analog path. |
Key Features
| Feature | Design Value |
|---|---|
| Zero-drift architecture | Eliminates 1/f noise and thermal drift - maintains sub-μV offset stability over time and temperature for decade-long calibration intervals. |
| 10-channel analog multiplexer | Reduces external signal routing complexity in multi-sensor systems (e.g., 8 RTDs + 2 calibration references) with single-chip front-end. |
| Internal calibration channels | Four factory-trimmed paths (GND, 0.1VCAL, 0.9VCAL, VREF) enable full-system offset/gain calibration without external switches or DACs. |
| Dual supply (AVDD/DVDD) | Prevents overvoltage damage to 3 V microcontroller ADCs when PGA is powered from 5 V - no level-shifting circuitry required. |
| SPI daisy-chain capability | Enables cascaded configuration of multiple PGA116AIPW devices using one SPI bus - cuts MCU GPIO count and PCB routing area. |
| Rail-to-rail input/output | Maximizes dynamic range utilization across supply rails - captures full sensor output swing (e.g., 0–5 V pressure transducer) without clipping. |
Applications
| Remote e-Meter Reading | Portable Data Acquisition |
|---|---|
Use Scenario: High-accuracy electricity metering in utility smart meters with multiple current/voltage sensors and temperature compensation. IC Role / Device Role / Timing Role: PGA116AIPW conditions low-level shunt resistor and CT outputs, selects channels via SPI, applies calibrated gain, and drives CDAC-based metrology ADCs. Use Value: 25 μV offset and 0.35 μV/°C drift ensure Class 0.2 meter accuracy across –25°C to 70°C field environments without periodic recalibration. | Use Scenario: Battery-powered handheld oscilloscope or multimeter capturing µV–V level signals from thermocouples, strain gauges, and pH probes. IC Role / Device Role / Timing Role: PGA116AIPW provides programmable gain, channel multiplexing, and system calibration before SAR ADC sampling. Use Value: 1.1 mA quiescent current and 4 μA shutdown extend AA battery life to >12 months in sleep mode; rail-to-rail I/O maximizes ADC utilization. |
| PC-Based Signal Acquisition Systems | Programmable Logic Controllers |
Use Scenario: USB-connected DAQ modules for lab testing, where PC software configures gain, channel, and calibration dynamically via SPI. IC Role / Device Role / Timing Role: PGA116AIPW serves as reconfigurable front-end with daisy-chain SPI enabling multi-channel expansion cards. Use Value: 10 MHz SPI and 200 ns gain switching allow real-time gain adaptation during waveform capture - no dead time between ranges. | Use Scenario: Industrial PLC analog input modules acquiring 4–20 mA loop signals, RTD temperatures, and voltage sensors across 16+ channels. IC Role / Device Role / Timing Role: PGA116AIPW multiplexes and conditions sensor inputs, performs on-board calibration, and interfaces to isolated ADCs. Use Value: Internal calibration channels reduce BOM cost by eliminating external precision references and relays; TSSOP-20 fits dense I/O module layouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PGA117AIPW | Scope gain set (1, 2, 5, 10, ..., 200) instead of binary; identical pinout, package, and feature set. | Better suited for applications requiring non-binary scaling (e.g., matching legacy 5× or 20× sensor gains). | Select PGA117AIPW only if scope gains are explicitly required; PGA116AIPW offers superior resolution for digital control loops needing exact 2ⁿ scaling. |
| AD8253ARMZ | 3-channel MUX, 10 MHz bandwidth, ±15 V supply capable; no internal calibration channels; SPI interface. | Targeted at higher-bandwidth industrial control (e.g., motor current sensing) rather than ultra-low-drift metrology. | Choose AD8253ARMZ for >100 kHz signal paths or bipolar supplies; PGA116AIPW remains preferred for sub-μV offset and integrated calibration in DC-coupled precision systems. |
Compared with PGA117AIPW, PGA116AIPW provides finer binary gain granularity (128× vs 200× max) and tighter DC specs; versus AD8253ARMZ, it trades bandwidth for zero-drift stability and on-chip calibration - making it optimal for static/low-frequency sensor systems demanding long-term accuracy.
Availability
PGA116AIPW is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and programmable logic controller applications requiring stable component supply, long-lifecycle support, and guaranteed traceability.
Supply support for PGA116AIPW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision signal chain solutions.
The PGA116AIPW belongs to TI's Zerø-Drift Programmable Gain Amplifier family, designed specifically for high-accuracy sensor signal conditioning in industrial, energy, and portable test equipment where offset, drift, and noise directly impact measurement integrity.
FAQ
What is the maximum SPI clock frequency supported by the PGA116AIPW?
The PGA116AIPW supports up to 10 MHz SPI clock frequency under recommended operating conditions (AVDD/DVDD = 2.2 V to 5.5 V). In daisy-chain configurations, the practical limit drops to 9.09 MHz due to cumulative DIN setup and DOUT propagation delays. The device implements SPI Mode 0,0 and requires tHI/tLO ≥40 ns at 10 MHz - verified per SBOS424C datasheet Section 7.6.
How does the PGA116AIPW handle calibration without external components?
The PGA116AIPW integrates four internal calibration channels tied to GND, 0.1VCAL, 0.9VCAL, and VREF - all accessible via SPI-controlled MUX selection. When VCAL is connected to a stable external reference, these paths enable full system offset and gain calibration without external switches, relays, or DACs. This capability is documented in the "Internal Calibration Channels" section of the PGA116AIPW datasheet (SBOS424C, Section 3).
Can the PGA116AIPW drive a 10 kΩ load while maintaining rail-to-rail output swing?
Yes - the PGA116AIPW delivers rail-to-rail output swing into a 10 kΩ load (RL = 10 kΩ // CL = 100 pF) with ±0.05 V headroom from each rail at ±0.25 mA load current. At ±5 mA, headroom increases to ±0.25 V. This performance is specified in the "Output" subsection of Electrical Characteristics (SBOS424C, Section 7.5) and validated across –40°C to 125°C.
What is the purpose of separate AVDD and DVDD supplies in the PGA116AIPW?
Separate AVDD (analog supply) and DVDD (digital/output stage supply) prevent digital switching noise from coupling into the analog signal path and avoid overvoltage damage to downstream 3 V ADCs when the PGA is powered from 5 V. The output stage is clamped to AVDD + 300 mV if AVDD < DVDD - a key protection feature detailed in the "Output" specification table (SBOS424C, Section 7.5).
Does the PGA116AIPW support hardware shutdown, and how does it differ from software shutdown?
Yes - the PGA116AIPW features a dedicated ENABLE pin (Pin 13) for hardware shutdown, pulling IQ to ≤1 μA when logic low. Software shutdown is activated via SPI register write and achieves ≤4 μA. Hardware shutdown is faster (2 μs disable time) and failsafe - essential for safety-critical power-down sequences independent of firmware execution. Both modes retain register contents (SBOS424C, Section 8.4).
PGA116AIPW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Programmable Gain
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 8V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 10 MHz
- Current - Input Bias:
- 1.5 nA
- Voltage - Input Offset:
- 75 µV
- Current - Supply:
- 330µA
- Current - Output / Channel:
- 60 mA
- Voltage - Supply Span (Min):
- 2.2 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
PGA116AIPW FAQ
1.How can I place an order for PGA116AIPW through Aetrix?
Please submit a Request for Quotation (RFQ) for PGA116AIPW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PGA116AIPW reliable?
The price and inventory of PGA116AIPW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PGA116AIPW is usually 5 days.
3.What payment methods are accepted for PGA116AIPW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PGA116AIPW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PGA116AIPW?
PGA116AIPW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PGA116AIPW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PGA116AIPW?
For technical support, including PGA116AIPW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PGA116AIPW requirements.
6.How does Aetrix verify that PGA116AIPW is sourced from the original manufacturer or authorized distributors?
All PGA116AIPW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PGA116AIPW meets industry standards.
7.What is the process for return or replacement of PGA116AIPW?
All PGA116AIPW units undergo pre-shipment inspection (PSI). If there is an issue with PGA116AIPW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PGA116AIPW part is unused and in its original packaging.
Return procedure for PGA116AIPW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PGA116AIPW Tags
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LM358DT
STMicroelectronics
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LM358DR
Texas Instruments
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LM2904DR
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MCP6006T-E/OT
Microchip Technology
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MCP6006UT-E/OT
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LM358P
Texas Instruments
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