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Texas Instruments PGA116AIPWG4
- Part No.:
- PGA116AIPWG4
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
PGA116AIPWG4.pdf
- Description:
- IC OPAMP PGA 1 CIRCUIT 20TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,166
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Product details
Overview
PGA116AIPWG4 from Texas Instruments is a zero-drift, 10-channel programmable gain amplifier (PGA) with integrated 10-input analog multiplexer, binary gain selection (1–128×), SPI daisy-chain interface, and rail-to-rail output. It delivers ±25 μV typical offset, 0.35 μV/°C drift, 12 nV/√Hz input noise, and operates from 2.2 V to 5.5 V dual supplies (AVDD/DVDD). It is used in high-precision data acquisition systems interfacing with CDAC-based ADCs.
For engineers reviewing the PGA116AIPWG4 datasheet, PGA116AIPWG4 pinout, PGA116AIPWG4 application, or PGA116AIPWG4 equivalent, key selection factors include its 10-channel MUX capability, hardware/software shutdown (IQ ≤4 μA), internal calibration channels (GND/0.1VCAL/0.9VCAL/VREF), and TSSOP-20 package compatibility with mixed-voltage microcontroller ADC interfaces.
Technical Context
The PGA116AIPWG4 implements a chopper-stabilized zero-drift architecture with auto-zeroing circuitry that corrects input offset and drift over temperature and time. Its 10-channel analog MUX feeds a single precision amplifier stage with programmable binary gains (1, 2, 4, 8, 16, 32, 64, 128) and supports both software (SPI command) and hardware (ENABLE pin) shutdown modes.
It features separate AVDD and DVDD supplies for analog and digital domains, enabling safe interfacing with lower-voltage microcontrollers (e.g., 3-V MSP430 ADC inputs) while powered from 5 V. The SPI interface operates up to 10 MHz and supports daisy-chain configuration via dedicated DIN/DOUT pins, eliminating need for individual CS lines across multiple devices.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Range | Binary gains: 1× to 128× - enables precise signal scaling before ADC without external resistors. |
| Input Offset Voltage | ±25 μV typical (±100 μV max) - ensures <0.1% error at 25 mV input when G=1. |
| Offset Drift | 0.35 μV/°C typical - maintains sub-μV stability across –40°C to 125°C industrial range. |
| Noise Density | 12 nV/√Hz @ f >10 kHz - supports low-noise measurement of small-signal sensors. |
| Supply Range | AVDD/DVDD = 2.2 V to 5.5 V - allows flexible dual-supply operation with independent voltage domains. |
| Channel Count | 10 analog inputs + 4 internal calibration channels - reduces external mux and reference components. |
| Shutdown Current | ≤4 μA (analog + digital) - extends battery life in portable instrumentation. |
Pinout & Package
Packaged in a 20-pin TSSOP (PW package), 6.50 mm × 4.40 mm body size, with exposed pad for thermal performance. Pinout validated per TI SBOS424C Rev C (2015).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 AVDD | Analog supply input | Provides power to analog front-end; must be bypassed with 0.1-μF ceramic capacitor. |
| 7 VCAL/CH0 | MUX channel 0 / calibration reference input | Connects to external low-impedance VCAL; selects internal CAL1–CAL4 channels (GND/0.1VCAL/0.9VCAL/VREF). |
| 8 VREF | Reference input | Sets output offset; requires ≥2 mA sourcing/sinking capability or connection to GND. |
| 9 VOUT | Analog output | Rail-to-rail swing (GND+50 mV to DVDD–50 mV @ ±0.25 mA); clamped to AVDD+300 mV if AVDD < DVDD. |
| 13 ENABLE | Hardware shutdown control | Logic low forces shutdown (IQ < 1 μA); complements SPI software shutdown command. |
| 14 GND | Analog/digital ground | Common return for AVDD, DVDD, and signal paths; critical for noise immunity and offset stability. |
| 15 SCLK | SPI clock input | Supports up to 10 MHz; timing compliant with SPI Mode 0,0 per Figure 1 in datasheet. |
| 16 DIN | SPI data input | Weak 10-μA pulldown enables daisy-chain use without external pull-down resistors. |
| 17 DOUT | SPI data output | High-impedance when CS is high; enables multi-device serial cascading. |
| 18 CS | SPI chip select | Active-low; initiates SPI frame; tCSH ≥40 ns required for reliable command latching. |
Key Features
| Feature | Design Value |
|---|---|
| Zero-drift architecture | Eliminates 1/f noise and long-term drift-critical for DC-coupled sensor conditioning over temperature. |
| Integrated 10-channel analog MUX | Reduces BOM count and PCB area vs discrete mux + PGA solutions; supports automatic channel scanning. |
| Dual supply (AVDD/DVDD) | Prevents overvoltage damage to 3-V microcontroller ADC inputs when PGA is powered from 5 V. |
| Four internal calibration channels | Enables system-level offset/gain calibration without external switches or references-improves production test efficiency. |
| SPI daisy-chain capability | Allows stacking multiple PGA116AIPWG4 units on one SPI bus-reduces GPIO usage and simplifies firmware. |
Applications
| Remote e-Meter Reading | Portable Data Acquisition |
|---|---|
|
Use Scenario: High-accuracy voltage/current measurement in smart electricity meters with anti-tampering requirements. IC Role / Device Role / Timing Role: Front-end PGA conditions shunt/sensor outputs prior to sigma-delta ADC conversion; handles 10-phase metering via MUX sequencing. Use Value: ±25 μV offset and 0.35 μV/°C drift ensure Class 0.2 meter accuracy across –25°C to 70°C operating range without recalibration. |
Use Scenario: Battery-powered handheld multimeter or environmental sensor logger capturing thermocouple, RTD, or bridge outputs. IC Role / Device Role / Timing Role: Programmable gain amplifies low-level sensor signals (e.g., 10 μV/°C thermocouple) to match ADC full-scale; MUX scans multiple sensors. Use Value: 12 nV/√Hz noise and rail-to-rail output enable >16-bit ENOB at 1 kSPS; 4 μA shutdown current extends 100-hour battery life. |
| PC-Based Signal Acquisition Systems | Programmable Logic Controllers |
|
Use Scenario: USB-connected DAQ modules for lab testing, where PC controls gain/channel selection via SPI. IC Role / Device Role / Timing Role: SPI-configurable PGA provides dynamic range adaptation across varying sensor types (strain gauge, pressure transducer, etc.). Use Value: Daisy-chain support allows up to 8 PGA116AIPWG4 units on one SPI bus-enabling 80-channel synchronized acquisition with single controller. |
Use Scenario: Modular I/O cards in industrial PLCs requiring high-accuracy analog input conditioning for process control loops. IC Role / Device Role / Timing Role: 10-channel MUX aggregates field sensor inputs; zero-drift performance ensures stable loop gain over extended ambient temperature swings. Use Value: Dual AVDD/DVDD supplies isolate noisy digital logic from sensitive analog paths-reducing EMI-induced offset errors in factory environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable gain amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PGA117AIPWG4 | Scope gain set (1×, 2×, 5×, 10×, 20×, 50×, 100×, 200×) instead of binary; otherwise identical pinout, MUX, and SPI interface. | Better suited for applications requiring non-binary scaling (e.g., matching legacy sensor output ranges or standard test equipment steps). | Select PGA117AIPWG4 when exact decade-based gain steps are needed; PGA116AIPWG4 preferred for digital control simplicity and binary-aligned firmware. |
| AD8253ARMZ | 3-channel MUX, 10-bit SPI interface, 10 MHz bandwidth, but no internal calibration channels; offset drift 1.5 μV/°C (max). | Lacks integrated calibration and 10-channel MUX-requires external components for system calibration and multi-sensor support. | Choose AD8253ARMZ only if higher bandwidth (>10 MHz) is mandatory and calibration is handled externally; PGA116AIPWG4 offers superior DC precision and integration. |
Compared with PGA117AIPWG4, PGA116AIPWG4 provides simpler binary gain control ideal for microcontroller firmware with bit-shift logic; versus AD8253ARMZ, it delivers 4× lower offset drift and eliminates external calibration hardware-reducing total system cost and layout complexity.
Availability
PGA116AIPWG4 is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and PC-based signal acquisition systems requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.
Supply support for PGA116AIPWG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision signal chain components.
The PGA116AIPWG4 belongs to TI's Zerø-Drift PGA family, designed specifically for high-accuracy, low-drift sensor signal conditioning in industrial, energy, and portable measurement applications.
FAQ
What is the maximum SPI clock frequency supported by PGA116AIPWG4?
The PGA116AIPWG4 supports SPI clock frequencies up to 10 MHz under standard single-device operation. In daisy-chain configurations, the maximum usable SCLK frequency is reduced to 9.09 MHz due to cumulative DIN setup time and DOUT propagation delay constraints across the chain. Timing compliance must be verified per Figure 61 in SBOS424C.
Does PGA116AIPWG4 require external calibration components?
No-PGA116AIPWG4 integrates four internal calibration channels (GND, 0.1VCAL, 0.9VCAL, VREF) accessible via its MUX. When VCAL is applied to the VCAL/CH0 pin, these channels enable full system-level offset and gain calibration without external switches, relays, or reference sources-reducing bill-of-materials and board space.
Can PGA116AIPWG4 drive a 10-kΩ load while maintaining rail-to-rail output swing?
Yes-PGA116AIPWG4 guarantees rail-to-rail output swing down to GND + 50 mV and up to DVDD – 50 mV when sourcing or sinking ±0.25 mA into a 10-kΩ load. At ±5 mA, output swing degrades to GND + 250 mV / DVDD – 250 mV. For full-scale 10-kΩ drive, ensure DVDD ≥ AVDD to avoid AVDD+300 mV clamping.
How does the dual AVDD/DVDD supply improve system robustness?
The separate AVDD and DVDD supplies in PGA116AIPWG4 prevent overvoltage damage to downstream 3-V microcontroller ADC inputs when the PGA is powered from 5 V. DVDD sets digital I/O levels, while AVDD powers the analog path-ensuring the output remains within the ADC's absolute maximum rating even during supply transients or brownouts.
What is the purpose of the ENABLE pin on PGA116AIPWG4?
The ENABLE pin (Pin 13) provides hardware-level shutdown control for PGA116AIPWG4. Driving it low places the device into ultra-low-power mode with total quiescent current ≤1 μA-complementing SPI software shutdown. This dual-mode capability enables fast wake-up (4 μs enable time) and failsafe power management in battery-critical systems.
PGA116AIPWG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Amplifier Type:
- Programmable Gain
- Number of Circuits:
- 1
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 8V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 10 MHz
- Current - Input Bias:
- 1.5 nA
- Voltage - Input Offset:
- 75 µV
- Current - Supply:
- 330µA
- Current - Output / Channel:
- 60 mA
- Voltage - Supply Span (Min):
- 2.2 V
- Voltage - Supply Span (Max):
- 5.5 V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
PGA116AIPWG4 FAQ
1.How can I place an order for PGA116AIPWG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for PGA116AIPWG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PGA116AIPWG4 reliable?
The price and inventory of PGA116AIPWG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PGA116AIPWG4 is usually 5 days.
3.What payment methods are accepted for PGA116AIPWG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PGA116AIPWG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PGA116AIPWG4?
PGA116AIPWG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PGA116AIPWG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PGA116AIPWG4?
For technical support, including PGA116AIPWG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PGA116AIPWG4 requirements.
6.How does Aetrix verify that PGA116AIPWG4 is sourced from the original manufacturer or authorized distributors?
All PGA116AIPWG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PGA116AIPWG4 meets industry standards.
7.What is the process for return or replacement of PGA116AIPWG4?
All PGA116AIPWG4 units undergo pre-shipment inspection (PSI). If there is an issue with PGA116AIPWG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PGA116AIPWG4 part is unused and in its original packaging.
Return procedure for PGA116AIPWG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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