Texas Instruments PGA117AIPW

Overview

PGA117AIPW from Texas Instruments is a zero-drift programmable gain amplifier with 10-channel analog multiplexer, SPI interface, and internal calibration channels. It delivers scope gains of 1, 2, 5, 10, 20, 50, 100, and 200; offset voltage ≤100 μV (max); drift ≤1.2 μV/°C (max); input noise density 12 nV/√Hz; and rail-to-rail output swing - enabling precision signal conditioning in battery-powered data acquisition systems.

For engineers reviewing the PGA117AIPW datasheet, PGA117AIPW pinout, PGA117AIPW application, or PGA117AIPW equivalent, key selection criteria include its 10-channel MUX capability, daisy-chain SPI support, hardware/software shutdown (IQ ≤4 μA), AVDD/DVDD dual-supply flexibility, and calibrated reference channels (GND, 0.1VCAL, 0.9VCAL, VREF) for system-level offset/gain correction.

Technical Context

The PGA117AIPW integrates a zero-drift chopper-stabilized amplifier core with a 10-input analog multiplexer and four internal calibration channels. Its SPI interface operates at up to 10 MHz with daisy-chain capability, supporting multi-device configurations without additional GPIO overhead.

It features separate AVDD (2.2–5.5 V) and DVDD (2.2–5.5 V) supplies, allowing safe interfacing with mixed-voltage systems - e.g., a 3-V microcontroller ADC while powered from 5-V rails. The ENABLE pin provides hardware shutdown, reducing total current to <1 μA.

Key Specifications

Pinout & Package

PGA117AIPW is housed in a 20-pin TSSOP (PW package), 6.50 mm × 4.40 mm body size, with exposed thermal pad (not electrically connected). Pin functions are validated per TI SBOS424C Rev. C (Nov. 2015).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable gain amplifier applications.

Compared with PGA116AIPW and AD8253ARMZ, PGA117AIPW uniquely combines scope-gain flexibility, on-chip calibration references, and daisy-chain SPI - reducing system-level calibration effort and enabling scalable multi-channel designs without external muxes or level shifters.

Availability

PGA117AIPW is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and PC-based signal acquisition systems requiring stable component supply, long-lifecycle support, and traceable sourcing.

Supply support for PGA117AIPW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision signal chain solutions.

PGA117AIPW belongs to TI's Zerø-Drift PGA product line, designed specifically for high-accuracy, low-power, multi-channel sensor signal conditioning in industrial, energy, and portable test equipment.

FAQ

What is the maximum SPI clock frequency supported by PGA117AIPW?

The PGA117AIPW supports an SPI clock frequency up to 10 MHz under recommended operating conditions (AVDD = DVDD = 2.2 V to 5.5 V). In daisy-chain configurations, the practical limit is 9.09 MHz due to cumulative DIN setup and DOUT propagation delays - verified in TI SBOS424C Figure 61. This allows fast reconfiguration of gain and channel settings during high-speed acquisition sequences in PGA117AIPW-based systems.

Does PGA117AIPW require external calibration components?

No, PGA117AIPW includes four internal calibration channels tied to GND, 0.1VCAL, 0.9VCAL, and VREF - eliminating need for external precision resistors or references. When VCAL is applied to pin 7 (VCAL/CH0), these channels enable automatic system-level offset and gain correction via SPI commands. This integrated capability reduces BOM cost and PCB area versus discrete calibration solutions used with PGA117AIPW alternatives.

How does PGA117AIPW handle supply voltage mismatch between AVDD and DVDD?

When AVDD < DVDD, PGA117AIPW clamps VOUT to AVDD + 300 mV to prevent overvoltage damage to downstream 3-V ADC inputs - a key protection feature documented in SBOS424C Section 7.5. This allows safe interfacing with mixed-supply systems (e.g., 5-V PGA driving 3-V MSP430 ADC) without external clamp diodes or level shifters, directly enhancing robustness in PGA117AIPW implementations.

What is the purpose of the ENABLE pin on PGA117AIPW?

Pin 13 (ENABLE) provides hardware-level shutdown control for PGA117AIPW: logic low reduces total supply current to <1 μA, complementing SPI-controlled software shutdown. This dual-mode control enables ultra-low-power sleep states in battery-operated devices - for example, waking the PGA117AIPW only during scheduled sensor reads. Unlike software-only shutdown, ENABLE guarantees immediate analog signal path disablement regardless of SPI state.

Can PGA117AIPW drive standard SAR ADC inputs directly?

Yes, PGA117AIPW delivers rail-to-rail output swing (GND + 50 mV to DVDD – 50 mV at ±0.25 mA), matching typical SAR ADC input ranges. Its low output impedance and 12 nV/√Hz noise ensure minimal SNR degradation - validated in TI's typical application circuits (SBOS424C Figure 43). When paired with CDAC-based ADCs, PGA117AIPW's optimized settling behavior further minimizes acquisition dead time in high-precision PGA117AIPW + ADC subsystems.