Texas Instruments PGA117AIPWR

Overview

PGA117AIPWR from Texas Instruments is a zero-drift programmable gain amplifier with 10-channel analog multiplexer, SPI interface, and internal calibration channels. It delivers scope gains of 1, 2, 5, 10, 20, 50, 100, and 200; offset voltage ≤100 μV (max); drift ≤1.2 μV/°C (max); rail-to-rail output swing; and operates from –40°C to +125°C. It is used in precision sensor signal conditioning for industrial metering and portable data acquisition.

For engineers reviewing the PGA117AIPWR datasheet, PGA117AIPWR pinout, PGA117AIPWR application, or PGA117AIPWR equivalent, key selection criteria include its 10-input MUX architecture, daisy-chain-capable SPI timing (10 MHz), dual supply support (AVDD/DVDD), internal calibration channel routing (GND/0.1VCAL/0.9VCAL/VREF), and guaranteed gain error ≤0.3% at G ≥50.

Technical Context

The PGA117AIPWR integrates a zero-drift chopper-stabilized amplifier core with a 10-channel analog multiplexer and four dedicated calibration inputs. Its SPI interface supports both standard and daisy-chain configurations, enabling multi-device synchronization without additional GPIO overhead.

It features separate AVDD (analog) and DVDD (digital/output stage) supplies, allowing safe interfacing with mixed-voltage systems-e.g., 5 V PGA driving a 3 V microcontroller ADC. Internal calibration channels are hardwired to GND, 0.1VCAL, 0.9VCAL, and VREF, enabling system-level offset/gain correction without external switches.

Key Specifications

Pinout & Package

TSSOP-20 package (6.50 mm × 4.40 mm), thermally enhanced for industrial ambient operation; pin-compatible with PGA116AIPWR (binary-gain variant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable gain amplifier applications.

Compared with PGA116AIPWR and AD8253ARMZ, the PGA117AIPWR uniquely combines decade-aligned scope gains, integrated calibration routing, and daisy-chain SPI - making it optimal for high-accuracy, multi-sensor industrial systems requiring minimal external components and deterministic calibration workflows.

Availability

PGA117AIPWR is available at Aetrix Electronics and suitable for remote e-meter reading, portable data acquisition, and programmable logic controller applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for PGA117AIPWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision signal chain solutions.

The PGA117 belongs to TI's Zerø-Drift Programmable Gain Amplifier family, designed specifically for high-accuracy sensor signal conditioning in industrial, energy, and portable test equipment where offset stability and gain linearity are critical.

FAQ

What is the maximum SPI clock frequency supported by the PGA117AIPWR?

The PGA117AIPWR supports SPI clock frequencies up to 10 MHz under standard single-device operation. In daisy-chain mode, the maximum usable SCLK frequency drops to 9.09 MHz due to cumulative DIN setup and DOUT propagation delays across the chain. This timing constraint is documented in Section 7.6 of the SBOS424C datasheet and ensures reliable register writes across multiple PGA117AIPWR devices without added timing margin.

Does the PGA117AIPWR require external calibration components?

No, the PGA117AIPWR does not require external calibration components for basic system-level calibration. Its four internal calibration channels (GND, 0.1VCAL, 0.9VCAL, VREF) are routed directly to the MUX and amplifier input, enabling software-controlled two-point offset/gain calibration using only the VCAL reference voltage applied to pin 7 (VCAL/CH0). External references are optional only for higher-precision VREF requirements.

How does the dual-supply architecture (AVDD/DVDD) benefit system design with the PGA117AIPWR?

The separate AVDD and DVDD supplies in the PGA117AIPWR isolate analog signal integrity from digital switching noise and prevent overvoltage damage to downstream ADCs. For example, when the PGA117AIPWR is powered from 5 V (AVDD = DVDD = 5 V) but interfaces with a 3 V microcontroller ADC, DVDD can be set to 3 V - ensuring VOUT remains within the ADC's absolute maximum input range while maintaining full analog performance on the AVDD rail.

Can the PGA117AIPWR drive an ADC input directly without external buffering?

Yes, the PGA117AIPWR is optimized to drive CDAC-type ADC inputs directly. Its rail-to-rail output stage delivers ±5 mA drive capability and maintains 0.0015% FSR nonlinearity into 10 kΩ//100 pF loads - matching typical SAR ADC input specifications. The internal RF/RI network (always connected between VOUT and VREF) further stabilizes settling behavior, eliminating the need for external series resistors or op-amp buffers in most precision acquisition designs.

What is the purpose of the ENABLE pin (Pin 13) on the PGA117AIPWR?

The ENABLE pin (Pin 13) provides hardware-level shutdown control for the PGA117AIPWR. When pulled low, it forces total supply current to ≤1 μA - significantly lower than the 4 μA typical achieved via SPI software shutdown alone. This dual-mode shutdown (hardware + software) enables robust power gating in battery-critical applications, such as wake-on-event sensor nodes, where leakage during deep sleep must be minimized independently of firmware state.