Texas Instruments PGA202KPG4
- Part No.:
- PGA202KPG4
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
PGA202KPG4.pdf
- Description:
- IC INST AMP 1 CIRCUIT 14DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,330
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PGA202KPG4 from Texas Instruments (formerly Burr-Brown) is a monolithic, digitally programmable instrumentation amplifier with fixed decade gains of 1, 10, 100, and 1000. It features FET inputs (50 pA max bias current), 2 µs settling time to 0.01%, 0.012% max nonlinearity, and 80 dB min CMRR. It is used in precision data acquisition front-ends where auto-ranging and dynamic range expansion are required.
For engineers reviewing the PGA202KPG4 datasheet, PGA202KPG4 pinout, PGA202KPG4 application, or PGA202KPG4 equivalent, key selection criteria include gain accuracy vs temperature (≤300 ppm/°C at G=1000), input offset drift (±(12 + 120/G) µV/°C), output swing (±10 V @ ±15 V supplies), digital interface compatibility (TTL/CMOS), and plastic DIP package suitability for commercial-temperature systems.
Technical Context
The PGA202KPG4 uses a differential transconductance front end with four laser-trimmed FET input stages, each selected via 2-bit digital control (A0/A1) to set gain without external components. Gain switching employs current-steering architecture to maintain near-constant bandwidth across gains - 1 MHz at G<1000 and 250 kHz at G=1000.
Its output stage is a differential transimpedance amplifier with output sense (pin 11) and reference (pin 4) terminals enabling remote load sensing and IR-drop compensation. The design eliminates resistor-matching dependence for CMRR, achieving ≥94 dB at G=1000, while internal laser trimming ensures initial gain error ≤0.1% and offset voltage ≤±(2 + 24/G) mV over 0°C to +70°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gain Options | 1, 10, 100, 1000 - discrete decade steps; no interpolation needed; selected by TTL/CMOS A0/A1 logic |
| Input Bias Current | 50 pA max at +25°C - enables high-impedance sensor interfacing (e.g., thermocouples) without significant DC error |
| Settling Time | 2 µs to 0.01% at G<1000 - supports rapid gain-switching in multiplexed DAQ systems |
| Nonlinearity | 0.012% max at G<1000 - ensures accurate amplitude scaling in measurement chains requiring <0.02% total harmonic distortion |
| CMRR | 94 dB min at G=1000 - maintains rejection of common-mode noise in noisy industrial environments |
| Supply Range | ±6 V to ±18 V - allows operation from standard ±12 V or ±15 V rails; quiescent current 6.5 mA typical |
| Temperature Range | 0°C to +70°C - commercial-grade specification matching plastic DIP (KP) package rating |
Pinout & Package
PGA202KPG4 is housed in a 14-pin plastic dual in-line package (PDIP-N), RoHS-compliant, with 2.54 mm lead pitch and through-hole mounting. Pin 1 is marked with a notch or dot; pin numbering follows standard DIP convention (counterclockwise from notch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 | Digital Input A0, A1 | 2-bit gain select lines referenced to Digital Common (pin 14); accept TTL/CMOS logic levels |
| 3 | +VIN | Non-inverting analog input; FET-buffered, 10 GΩ || 1 pF impedance |
| 4 | VREF | Reference terminal for output common; connects to load ground to eliminate IR drop error |
| 5, 6 | Filter A, Filter B | Internal summing node access points; allow external capacitors (e.g., 47–525 pF) to reduce bandwidth/noise |
| 7 | –VCC | Negative supply rail; absolute max –18 V; requires local 1 µF tantalum decoupling |
| 8 | +VCC | Positive supply rail; absolute max +18 V; requires local 1 µF tantalum decoupling |
| 9 | VADJ | Output offset adjustment terminal; used with external potentiometer (e.g., 100 kΩ) for fine calibration |
| 10 | Filter B | Duplicate access to same internal node as pin 5; provided for layout flexibility |
| 11 | VSENSE | Output sense feedback point; connect directly to load to close loop around wiring resistance |
| 12 | VOUT | Main output; capable of ±10 V swing into 10 kΩ load; supports current boosting via external op amp |
| 13 | –VIN | Inverting analog input; matched to pin 3; differential input voltage drives transconductance stage |
| 14 | Digital Common | Digital ground reference; may be tied to analog ground or isolated up to 8 V below +VCC |
Key Features
| Feature | Design Value |
|---|---|
| Laser-trimmed gain and offset | Eliminates need for external calibration components; achieves ≤0.1% initial gain error and ≤±(2 + 24/G) mV offset over 0°C to +70°C |
| FET-input architecture | Delivers 50 pA max input bias current, enabling direct connection to high-Z sources (e.g., pH electrodes, piezoelectric sensors) without signal degradation |
| Digital gain control interface | TTL/CMOS-compatible A0/A1 inputs simplify microcontroller integration; no level-shifting or additional logic required |
| Output sense and reference terminals | Enable 4-wire Kelvin sensing at the load, removing voltage drop errors from PCB traces or connectors in precision applications |
| Transconductance-based front end | Maintains stable bandwidth across gain settings - 1 MHz at G=10 and G=100 - critical for consistent settling in auto-ranging systems |
Applications
| Data Acquisition Systems | Auto-Ranging Circuits |
|---|---|
Use Scenario: High-resolution ADC front-end in benchtop multimeters and modular DAQ modules. IC Role / Device Role / Timing Role: Programmable-gain instrumentation amplifier conditioning low-level sensor outputs before digitization. Use Value: Enables single ADC to handle ±10 mV to ±10 V inputs with consistent 16-bit+ ENOB across ranges, reducing system component count. |
Use Scenario: Real-time gain adaptation in oscilloscope vertical amplifiers and spectrum analyzers. IC Role / Device Role / Timing Role: Digitally switched gain block that reconfigures within 2 µs to preserve waveform fidelity during amplitude transitions. Use Value: Maintains signal integrity during fast transients; avoids clipping or under-utilization of ADC full-scale range. |
| Dynamic Range Expansion | Remote Instrumentation |
Use Scenario: Low-noise signal conditioning in seismic sensor arrays and acoustic emission monitoring. IC Role / Device Role / Timing Role: Front-end amplifier with selectable gain to resolve microvolt-level events amid varying background noise floors. Use Value: Extends effective dynamic range beyond 120 dB by combining low 1.7 µVP-P 0.1–10 Hz noise with precise decade gain steps. |
Use Scenario: Signal conditioning in distributed environmental monitoring nodes (e.g., water quality, air pollution). IC Role / Device Role / Timing Role: Isolated, low-power instrumentation amplifier interfacing with RTD/thermocouple sensors over long cables. Use Value: Output sense (pin 11) and VREF (pin 4) compensate for line resistance up to several ohms, preserving accuracy without calibration per node. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable-gain instrumentation amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| INA118P | Analog gain control (external resistor); no digital interface; 10 µs settling; 0.002% nonlinearity | Suitable for static-gain, ultra-precision applications; lacks auto-ranging capability | Select when digital control is unnecessary and lowest possible offset drift (0.1 µV/°C) is prioritized over speed |
| PGA205AU | Binary gain steps (1, 2, 4, 8, 16); SOIC-16 package; 0.005% nonlinearity; 1.5 µs settling | Better suited for compact PCB layouts and higher-speed binary-scaled systems (e.g., motor current sensing) | Select when binary gain progression matches control firmware and surface-mount assembly is preferred over through-hole PDIP |
Compared with PGA202KPG4, INA118P trades digital programmability for superior DC precision and lower cost in fixed-gain roles, while PGA205AU offers faster settling and SMT packaging but lacks the decade gain structure essential for logarithmic-range scaling in test equipment.
Availability
PGA202KPG4 is available at Aetrix Electronics and suitable for data acquisition systems, auto-ranging circuits, and remote instrumentation requiring stable component supply across commercial temperature ranges and long-lifecycle production programs.
Supply support for PGA202KPG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments (TI) is a global semiconductor leader specializing in analog and embedded processing technologies, with deep heritage in precision amplifiers dating to Burr-Brown's acquisition in 2000.
The PGA202KPG4 belongs to TI's legacy programmable-gain instrumentation amplifier product line, engineered specifically for high-accuracy, digitally controlled signal conditioning in test and measurement equipment where gain agility and low drift are critical.
FAQ
What is the maximum operating temperature for the PGA202KPG4?
The PGA202KPG4 is specified for operation from 0°C to +70°C, consistent with its plastic DIP (KP) package rating. While the device can survive junction temperatures up to 175°C, sustained operation above +70°C is not guaranteed for parametric performance - including gain error (≤300 ppm/°C at G=1000), offset drift (±(12 + 120/G) µV/°C), and CMRR (≥94 dB). For extended temperature use, consider ceramic-package variants like PGA202AG.
Does the PGA202KPG4 require external components for basic operation?
No, the PGA202KPG4 requires no external resistors or capacitors for core functionality. Laser trimming ensures accurate gain (≤0.1% error) and offset (≤±(2 + 24/G) mV) across all four decade settings. Only decoupling capacitors (1 µF tantalum per supply rail) are recommended for stability. Optional components - such as an external potentiometer on VADJ (pin 9) or filter capacitors on Filter A/B (pins 5/10) - serve calibration or bandwidth tailoring, not fundamental operation.
How does the output sense (VSENSE) pin improve measurement accuracy in the PGA202KPG4?
The VSENSE pin (pin 11) provides a dedicated feedback path from the load back to the output amplifier, enabling true 4-wire (Kelvin) sensing. When connected directly to the load terminal, it eliminates voltage drop errors caused by trace or connector resistance between the PGA202KPG4 output and the load. This ensures the amplifier regulates VOUT precisely at the load point - critical for maintaining gain accuracy in systems with >1 Ω series resistance, such as long-cable remote sensor interfaces.
Can the PGA202KPG4 interface directly with a 3.3V microcontroller?
Yes - the PGA202KPG4's digital inputs (A0, A1, and Digital Common) accept TTL/CMOS logic levels and tolerate Digital Common voltages from –VCC to (VCC – 8 V). With ±15 V supplies, Digital Common can be tied to 0 V (shared with MCU ground), allowing direct connection of 3.3 V GPIO outputs to A0/A1. No level shifters are needed, as the inputs draw only 10 µA and recognize >2.4 V as logic high and <0.8 V as logic low.
What is the purpose of the Filter A and Filter B pins on the PGA202KPG4?
Filter A (pin 5) and Filter B (pin 10) provide access to internal summing nodes of the output amplifier, allowing external capacitors (e.g., 47–525 pF) to be added in parallel with internal 5.3 pF elements. This reduces bandwidth - from 1 MHz (no cap) to 10 kHz (525 pF) - lowering integrated output noise at the cost of slower settling. It is a design trade-off used in low-frequency, high-dynamic-range applications like vibration analysis or precision weigh scales where noise dominates over speed.
PGA202KPG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- Instrumentation
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 20V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 1 MHz
- Current - Input Bias:
- 10 pA
- Voltage - Input Offset:
- 500 µV
- Current - Supply:
- 6.5mA
- Current - Output / Channel:
- -
- Voltage - Supply Span (Min):
- 12 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- -25°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-PDIP
PGA202KPG4 FAQ
1.How can I place an order for PGA202KPG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for PGA202KPG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PGA202KPG4 reliable?
The price and inventory of PGA202KPG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PGA202KPG4 is usually 5 days.
3.What payment methods are accepted for PGA202KPG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PGA202KPG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PGA202KPG4?
PGA202KPG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PGA202KPG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PGA202KPG4?
For technical support, including PGA202KPG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PGA202KPG4 requirements.
6.How does Aetrix verify that PGA202KPG4 is sourced from the original manufacturer or authorized distributors?
All PGA202KPG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PGA202KPG4 meets industry standards.
7.What is the process for return or replacement of PGA202KPG4?
All PGA202KPG4 units undergo pre-shipment inspection (PSI). If there is an issue with PGA202KPG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PGA202KPG4 part is unused and in its original packaging.
Return procedure for PGA202KPG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PGA202KPG4 Tags

-
LM358DT
STMicroelectronics

-
LM358DR
Texas Instruments

-
LM2904DR
Texas Instruments

-
LM358ADR
Texas Instruments
-
LM2904DGKR
Texas Instruments
-
LM324DR
Texas Instruments

-
MCP6006T-E/OT
Microchip Technology

-
MCP6006UT-E/OT
Microchip Technology

-
LM324PWR
Texas Instruments

-
LM2902PWR
Texas Instruments
-
LM2902DR
Texas Instruments

-
LM358P
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

