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Texas Instruments PGA205AU
- Part No.:
- PGA205AU
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
PGA205AU.pdf
- Description:
- IC INST AMP 1 CIRCUIT 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,910
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Product details
Overview
PGA205AU from Texas Instruments (formerly Burr-Brown) is a digitally programmable gain instrumentation amplifier with fixed binary gains of 1, 2, 4, and 8 V/V, ±50 µV max input offset voltage, 0.25 µV/°C drift, and 16-pin SOIC (DW) surface-mount package rated for –40°C to +85°C operation. It serves as a precision front-end signal conditioner in data acquisition systems interfacing low-level sensor outputs.
For engineers reviewing the PGA205AU datasheet, PGA205AU pinout, PGA205AU application, or PGA205AU equivalent, key selection criteria include its digital gain control via TTL/CMOS-compatible A0/A1 inputs, ±40V input overvoltage protection, 100 kHz bandwidth at G=8, and laser-trimmed accuracy enabling direct connection to bridge sensors and thermocouples without external trimming.
Technical Context
The PGA205AU implements a three-op-amp instrumentation architecture with digitally switched internal feedback networks (25 kΩ resistors per gain stage), enabling discrete gain selection without external components. Its input stage (A1/A2) provides high common-mode rejection (up to 112 dB at G=8), while the output difference amplifier (A3) delivers rail-to-rail compatible swing with ±1.3 V headroom from supply rails.
Digital inputs A0 and A1 directly interface TTL/CMOS logic without requiring a separate logic supply; digital ground (pin 14) is configurable between V– and (V+)–4 V. Gain switching is asynchronous and immediate-no latching required-with settling time of 28 µs (0.01%) at G=8, and overload recovery in 70 µs after 50% overdrive.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Gains | 1, 2, 4, 8 V/V - discrete binary steps selected by A0/A1 logic states; no interpolation or analog tuning. |
| Input Offset Voltage | ±50 µV max - laser-trimmed input stage enables <0.5 mV total error at G=8 for ±100 mV input signals. |
| CMRR | 112 dB at G=8 - ensures >80 dB rejection of 60 Hz interference when measuring µV-level differential signals on noisy PCBs. |
| Bandwidth (–3 dB) | 100 kHz at G=8 - supports sampling of dynamic sensor signals up to ~30 kHz with minimal amplitude loss. |
| Input Protection | ±40 V absolute max - survives transient surges from industrial sensors or miswired field connections without damage. |
| Supply Range | ±4.5 V to ±18 V - operates from dual batteries (±5 V) or industrial rails (±15 V); quiescent current 5.2 mA typ at ±15 V. |
| Package | SOIC-16 (DW) - surface-mount footprint compatible with automated assembly; MSL Level-3, 260°C reflow profile. |
Pinout & Package
SOL-16 surface-mount package (Texas Instruments SOIC-DW, 16-pin, 7.5 mm × 10.3 mm body, 1.27 mm pitch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VO1) | Output of first input amplifier (A1) | Internal node; not user-accessible - used only for internal feedback and overvoltage protection. |
| 2, 3 (NC) | No internal connection | Unbonded die pads; must remain unconnected on PCB. |
| 4 (V–IN) | Inverting input terminal | Accepts differential input voltage; requires bias current return path (e.g., matched resistors to Ref or ground). |
| 5 (V+IN) | Non-inverting input terminal | Accepts differential input voltage; same bias current requirements as V–IN. |
| 6, 7 (VOS Adj) | Input offset trim terminals | Laser-trimmed; external adjustment optional - use only for input-stage nulling at highest gain. |
| 8 (V–) | Negative power supply | Must be decoupled locally with ≥1 µF capacitor; supports operation down to –4.5 V. |
| 9 (VO2) | Output of second input amplifier (A2) | Internal node; not user-accessible - used only for internal feedback and overvoltage protection. |
| 10 (Ref) | Output reference terminal | Defines output common-mode level; must connect to low-impedance ground or buffered reference to maintain CMRR >100 dB. |
| 11 (VO) | Main output terminal | Delivers G × (V+IN – V–IN) + VREF; capable of ±13.7 V swing on ±15 V supplies. |
| 12 (Feedback) | Output feedback sense | Must connect directly to VO (pin 11); enables remote sensing at load to eliminate PCB trace IR drop errors. |
| 13 (V+) | Positive power supply | Must be decoupled locally with ≥1 µF capacitor; supports operation up to +18 V. |
| 14 (Dig. Ground) | Digital ground reference | Reference for A0/A1 logic levels; can be tied to analog ground or isolated to prevent digital noise coupling. |
| 15 (A0) | Gain select address bit 0 | TTL/CMOS-compatible input; logic high = >2 V above Dig. Ground; selects LSB of gain code (G=1,2,4,8). |
| 16 (A1) | Gain select address bit 1 | TTL/CMOS-compatible input; logic high = >2 V above Dig. Ground; selects MSB of gain code (G=1,2,4,8). |
Key Features
| Feature | Design Value |
|---|---|
| Digital gain control without logic supply | A0/A1 accept standard TTL/CMOS voltages referenced to user-defined digital ground - eliminates need for dedicated 5 V logic rail. |
| ±40 V input overvoltage protection | Withstands industrial transients and wiring faults on either input independently - no external clamps or series resistors required. |
| Laser-trimmed 0.25 µV/°C offset drift | Enables stable DC measurements over temperature without recalibration - critical for medical and weigh-scale applications. |
| 100 kHz bandwidth at G=8 | Supports high-speed sensor readout (e.g., strain gauge impact testing) while maintaining 8-bit effective resolution at 100 kSPS. |
| Configurable Ref and Feedback pins | Ref sets output common-mode; Feedback enables Kelvin sensing at load - together they support precision closed-loop transducer interfaces. |
Applications
| Bridge Sensor Interface | Medical ECG Front-End |
|---|---|
Use Scenario: Amplifying mV-level differential output from a 350 Ω Wheatstone bridge under varying temperature and EMI conditions. IC Role / Device Role / Timing Role: Precision instrumentation amplifier providing programmable gain (G=1 to 8) and common-mode rejection before ADC digitization. Use Value: ±40 V input protection prevents damage during sensor cable disconnect events; laser-trimmed offset ensures <1 µV baseline drift over 8-hour clinical monitoring. | Use Scenario: Conditioning low-amplitude, high-impedance biopotential signals from Ag/AgCl electrodes with 60 Hz notch filtering. IC Role / Device Role / Timing Role: First-stage gain block with selectable gain (G=1 for calibration, G=8 for weak signals) and ultra-low noise (0.5 µVp-p, 0.1–10 Hz). Use Value: Input bias current <2 nA avoids electrode polarization; CMRR >110 dB suppresses mains interference without active guarding. |
| Industrial Data Acquisition | Thermocouple Signal Conditioning |
Use Scenario: Multiplexed analog input module acquiring signals from 16 RTDs, thermocouples, and voltage sources in a PLC backplane. IC Role / Device Role / Timing Role: Channel-specific programmable gain stage enabling unified 16-bit ADC input range across diverse sensor types. Use Value: Digital gain selection via FPGA-controlled A0/A1 allows per-channel optimization; SOIC-16 package fits high-density I/O card layouts. | Use Scenario: Cold-junction compensated K-type thermocouple measurement with linearization in firmware. IC Role / Device Role / Timing Role: High-Z, low-drift amplifier boosting µV/°C thermocouple output prior to cold-junction compensation and digitization. Use Value: Input common-mode range extends to ±12.7 V - accommodates wide ambient temperature swings without input saturation; VOS Adj pins allow factory calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable-gain instrumentation amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| INA128UA | Fixed gain (5–10,000 V/V via single resistor); no digital control; lower bandwidth (1.3 MHz at G=100) but better noise (0.8 nV/√Hz). | Requires manual gain configuration per channel; unsuitable for dynamically reconfigured DAQ systems. | Select when static gain and maximum AC performance outweigh need for digital reconfiguration. |
| AD8253ARMZ | Pin-compatible 16-pin SOIC; gains 1/2/4/8/16/32/64/128 V/V; SPI interface instead of parallel A0/A1; integrated reference buffer. | Requires SPI controller overhead but supports finer gain resolution and daisy-chaining of multiple devices. | Select when system already uses SPI peripherals and requires >8 gain steps or synchronized multi-channel gain updates. |
Compared with INA128UA and AD8253ARMZ, the PGA205AU uniquely balances simple parallel digital control, robust ±40 V input tolerance, and SOIC-16 compatibility - making it optimal for cost-sensitive, high-reliability industrial DAQ where gain changes occur infrequently and ESD/transient immunity is critical.
Availability
PGA205AU is available at Aetrix Electronics and suitable for industrial data acquisition, medical instrumentation, and bridge-based sensor conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for PGA205AU includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired Burr-Brown in 2000 and maintains full production and support for legacy precision analog products including the PGA204/205 family.
The PGA205AU belongs to TI's precision instrumentation amplifier product line, designed specifically for high-accuracy, low-drift signal conditioning in sensor interface applications where programmable gain, input protection, and temperature stability are essential.
FAQ
What gain settings does the PGA205AU support, and how are they selected?
The PGA205AU supports four discrete binary gains: 1, 2, 4, and 8 V/V. These are selected using two TTL/CMOS-compatible digital inputs - A0 (pin 15) and A1 (pin 16). The gain code is decoded as follows: A1=0/A0=0 → G=1; A1=0/A0=1 → G=2; A1=1/A0=0 → G=4; A1=1/A0=1 → G=8. No external components or logic supply are needed - digital ground (pin 14) may be tied to system ground or a separate low-noise reference.
Does the PGA205AU require external components for basic operation?
No, the PGA205AU operates with zero external components for core functionality: gain selection is handled internally via laser-trimmed 25 kΩ feedback resistors, and input protection is built-in. However, best practice requires local 1 µF decoupling capacitors on V+ (pin 13) and V– (pin 8), a low-impedance connection from Ref (pin 10) to ground or reference, and a direct short between Feedback (pin 12) and VO (pin 11). External offset trim is optional and only recommended for high-precision DC applications.
Can the PGA205AU be used with single-supply operation?
No - the PGA205AU is specified exclusively for dual-supply operation (±4.5 V to ±18 V). Its input common-mode range and output swing are centered around ground, and the internal architecture relies on symmetric positive/negative rails. Attempting single-supply operation (e.g., 0 V and +15 V) will result in input saturation, degraded CMRR, and failure to meet datasheet specifications. For single-supply applications, consider TI's INA333 or ADI's AD8420.
What is the purpose of the VOS Adj pins (6 and 7) on the PGA205AU?
Pins 6 and 7 are dedicated input offset voltage adjustment terminals for the first-stage amplifiers (A1 and A2). They enable fine-tuning of input-stage offset - typically performed at G=8 with inputs grounded - to achieve sub-10 µV residual offset. This adjustment does not affect output-stage offset or drift. The PGA205AU is laser-trimmed to ±50 µV max, so external trimming is optional and recommended only for applications demanding <5 µV total input-referred offset over temperature.
How does the PGA205AU handle input overvoltage conditions?
The PGA205AU features fully independent ±40 V overvoltage protection on both V+IN (pin 5) and V–IN (pin 4). This means either input can withstand –40 V to +40 V relative to ground - even with no power applied - without damage or parametric shift. Internal protection circuitry limits input current to ~1.5 mA during overload, eliminating the need for external series resistors or clamps. This capability is validated per absolute maximum ratings and is intrinsic to the die design.
PGA205AU Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Amplifier Type:
- Instrumentation
- Number of Circuits:
- 1
- Output Type:
- -
- Slew Rate:
- 0.7V/µs
- Gain Bandwidth Product:
- -
- -3db Bandwidth:
- 1 MHz
- Current - Input Bias:
- 500 pA
- Voltage - Input Offset:
- 25 µV
- Current - Supply:
- 5.2mA
- Current - Output / Channel:
- 23 mA
- Voltage - Supply Span (Min):
- 9 V
- Voltage - Supply Span (Max):
- 36 V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
PGA205AU FAQ
1.How can I place an order for PGA205AU through Aetrix?
Please submit a Request for Quotation (RFQ) for PGA205AU on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PGA205AU reliable?
The price and inventory of PGA205AU are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PGA205AU is usually 5 days.
3.What payment methods are accepted for PGA205AU?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PGA205AU transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PGA205AU?
PGA205AU orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PGA205AU order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PGA205AU?
For technical support, including PGA205AU datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PGA205AU requirements.
6.How does Aetrix verify that PGA205AU is sourced from the original manufacturer or authorized distributors?
All PGA205AU products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PGA205AU meets industry standards.
7.What is the process for return or replacement of PGA205AU?
All PGA205AU units undergo pre-shipment inspection (PSI). If there is an issue with PGA205AU, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PGA205AU part is unused and in its original packaging.
Return procedure for PGA205AU:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PGA205AU Tags
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