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Diodes Incorporated PI2EQX5904NJEX
- Part No.:
- PI2EQX5904NJEX
- Manufacturer:
- Diodes Incorporated
- Category:
- Signal Buffers, Repeaters, Splitters
- Package:
- 100-LBGA
- Datasheet:
-
PI2EQX5904NJEX.pdf
- Description:
- IC REDRIVER PCIE 4CH 100LBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,042
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Product details
Overview
PI2EQX5904NJEX from Diodes Incorporated is a PCIe® 2.0-compliant 4-lane (8-channel) serial ReDriver™ with programmable equalization (up to 12.3 dB @2.5 GHz), adjustable transmitter de-emphasis (–8.5 dB max), and 1.2 V single-supply operation. It supports electrical idle, receiver detect, loopback/mux/demux modes, and operates across –40°C to +85°C for backplane and cable extension in server blade interconnects.
For engineers reviewing the PI2EQX5904NJEX datasheet, PI2EQX5904NJEX pinout, PI2EQX5904NJEX application, or PI2EQX5904NJEX equivalent, key selection criteria include CML I/O compatibility, per-group equalization/de-emphasis control (A/B channel banks), 100-contact LBGA package thermal performance, and I²C vs. pin-strapped configuration trade-offs for PCIe signal integrity tuning.
Technical Context
The PI2EQX5904NJEX implements dual independent CML channel banks (A and B), each comprising four differential lanes with dedicated equalizer, output swing, and de-emphasis controls. Its input equalization compensates for insertion loss-induced ISI up to 12.3 dB at 2.5 GHz, while output de-emphasis applies pre-compensation up to –8.5 dB using three-bit D[0:2]_A/B strapping or I²C registers.
Configuration is managed via MODE pin selection between static pin-strapping (SEL[0:2], S[0:1], D[0:2]) and dynamic I²C control (7-bit address, 100 kbps, A0/A1/A4 programmable). Loopback, receiver detect (RX50_A/B), and signal detect (SIG_A/B) are hardware-asserted outputs enabling automated lane enablement and test-mode validation without host intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 5.0 Gbps per lane - supports full PCIe 2.0 specification compliance with BER optimization. |
| Supply Voltage | 1.2 V ± 0.05 V - tight tolerance enables stable low-power operation and reduces supply noise coupling into high-speed analog paths. |
| Power Consumption | 660 mW typical - enables thermal management in dense 1U/2U server blade environments with minimal heatsinking. |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade embedded server and storage controller applications. |
| Equalization Range | 0.5 dB to 12.3 dB @2.5 GHz - eight discrete settings allow precise compensation for varying trace lengths and loss profiles. |
| De-emphasis Range | 0 dB to –8.5 dB - seven-step adjustment optimizes eye opening at receiver after long PCB traces or cables. |
| I²C Interface | 7-bit address, 100 kbps standard mode - supports up to eight devices on one bus with A0/A1/A4 pin-programmable addressing. |
Pinout & Package
Package: 100-contact LBGA (11 mm × 11 mm, 0.8 mm pitch), Pb-free and RoHS-compliant, designed for high-density server motherboard layouts with controlled impedance routing and thermal pad grounding.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0RX+/A0RX− | CML Input (Channel A0) | Differential receiver pair with 50 Ω internal pull-down during normal operation; >200 kΩ otherwise for low-power idle detection. |
| A0TX+/A0TX− | CML Output (Channel A0) | Differential driver pair with 50 Ω internal pull-up during active drive; 2 kΩ pull-up in Hi-Z states for electrical idle support. |
| DE_A | De-emphasis Enable (Group A) | LVCMOS input controlling half-bit vs. full-bit de-emphasis mode for all four A-lanes; internal 100 kΩ pull-up. |
| SEL0_A–SEL2_A | Equalization Control (Group A) | Three-pin strap selecting one of eight equalization levels (0.5–12.3 dB); latched at power-on or updated via I²C when MODE = low. |
| PD# | Power-Down Input | Active-low global shutdown: drives all inputs/outputs to Hi-Z, reducing system standby power; internal 100 kΩ pull-up. |
| LB# | Loopback Mode Select | Active-low control enabling per-lane loopback, broadcast, mux, or demux configurations; not intended for runtime switching. |
| RXD_A | Receiver Detect Enable (Group A) | Enables automatic 50 Ω load sensing on A-group outputs; RX50_A asserts high when termination is detected. |
| SCL/SDA | I²C Interface | 3.3 V tolerant bidirectional bus interface for dynamic register programming; supports multi-device addressing via A0/A1/A4 pins. |
Key Features
| Feature | Design Value |
|---|---|
| Per-group equalization & de-emphasis | Independent A/B bank control allows asymmetric tuning for mixed-length trace topologies (e.g., A-lanes to CPU, B-lanes to switch). |
| Electrical Idle support | Input level detect forces outputs to Hi-Z with internal pull-ups, meeting PCIe L0s state requirements without external logic. |
| Hardware-assisted receiver detection | RX50_A/B outputs directly indicate presence of 50 Ω termination, enabling automatic lane enumeration and power gating. |
| Configurable loopback/mux/demux | LB# pin and I²C registers enable test-mode signal routing (e.g., A0Rx→B0Tx) for board-level validation without FPGA reconfiguration. |
| Low-power standby mode | PD# pin disables entire IC with <1 µA quiescent current, supporting hot-plug and energy-efficient server power states. |
Applications
| Server Blade Interconnect | PCIe Backplane Extension |
|---|---|
|
Use Scenario: High-density 2U/4U rack servers with modular compute blades connected via midplane PCIe 2.0 fabric. IC Role / Device Role / Timing Role: Signal ReDriver™ placed between ASIC and midplane connector to restore signal integrity degraded by 12+ inch FR4 traces and multiple vias. Use Value: Enables reliable 5.0 Gbps link training across 16+ layers and 3+ connectors per lane, reducing bit error rate below 10⁻¹² without retiming. |
Use Scenario: Enterprise storage chassis with front-panel NVMe U.2/U.3 drives routed through long backplane traces (>15 cm). IC Role / Device Role / Timing Role: Lane-specific equalization and de-emphasis applied before and after backplane to compensate for frequency-dependent loss. Use Value: Maintains PCIe 2.0 eye margin >200 mVpp at receiver despite 18 dB insertion loss at 2.5 GHz, eliminating need for costly low-loss laminates. |
| Cable Adapter Module | Embedded Controller Expansion |
|
Use Scenario: Active copper cable assemblies (e.g., QSFP+ to PCIe x4 breakout) used in GPU-accelerated workstations. IC Role / Device Role / Timing Role: ReDriver™ integrated into cable module PCB to extend reach beyond passive cable limits (≥3 m at 5 Gbps). Use Value: Supports full PCIe 2.0 bandwidth over cost-effective twinaxial cable by correcting jitter accumulation and amplitude roll-off. |
Use Scenario: Industrial PC with PCIe expansion slot driving FPGA-based vision processing card over extended carrier board traces. IC Role / Device Role / Timing Role: Local signal conditioning at FPGA side to offset trace loss from 8-layer motherboard routing to edge connector. Use Value: Eliminates need for expensive retimers or custom layout revisions by restoring signal integrity with <10 ps added jitter. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe 2.0 ReDriver™ applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PI3EQX8904 | Successor device with identical 100-LBGA footprint, enhanced 6.0 Gbps PCIe 3.0 support, and lower 550 mW typical power. | Required for new designs targeting PCIe 3.0 endpoints or backward-compatible systems needing future-proofing. | Select PI3EQX8904 for new designs; PI2EQX5904NJEX remains viable for legacy PCIe 2.0-only platforms with existing qualification. |
| TI TUSB1002A | USB 3.1 Gen 1/PCIe 2.0 dual-mode ReDriver™ with integrated USB Type-C switch logic and 1.8 V I/O tolerance. | Used in hybrid docking stations requiring simultaneous USB and PCIe lane extension, not pure PCIe-only systems. | Choose only if co-routing USB 3.1 and PCIe 2.0 signals is required; lacks PI2EQX5904's dedicated PCIe receiver detect and loopback modes. |
Compared with PI3EQX8904, PI2EQX5904NJEX offers proven stability in mature PCIe 2.0 deployments but lacks PCIe 3.0 readiness; versus TUSB1002A, it delivers superior PCIe-specific features (RXD/SIG outputs, per-bank tuning) at the cost of USB functionality.
Availability
PI2EQX5904NJEX is available at Aetrix Electronics and suitable for server blade interconnects, PCIe backplane extensions, active cable modules, and embedded controller expansion requiring stable component supply and long-term industrial temperature support.
Supply support for PI2EQX5904NJEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and connectivity applications.
The PI2EQX5904NJEX belongs to Diodes' PCIe ReDriver™ product line, engineered specifically to solve high-speed signal degradation in enterprise server, storage, and communications infrastructure where low latency and deterministic timing are critical.
FAQ
Is PI2EQX5904NJEX pin-compatible with PI3EQX8904?
Yes - PI2EQX5904NJEX and PI3EQX8904 share identical 100-contact LBGA mechanical footprint and pin mapping, enabling drop-in replacement in existing PCB layouts. However, PI3EQX8904 introduces PCIe 3.0 support and updated I²C register definitions, so firmware must be validated for full feature compatibility.
How does receiver detect (RXD) function without I²C communication?
RXD_A and RXD_B are LVCMOS inputs that enable or disable hardware-based 50 Ω load sensing on their respective channel groups. When asserted low, receiver detect is disabled and outputs default to 2 kΩ pull-up; when high, the IC autonomously monitors output pins and asserts RX50_A/B high upon detecting valid 50 Ω termination - no I²C interaction required.
What is the purpose of the LB# pin, and can it be toggled dynamically?
LB# is an active-low pin enabling loopback, broadcast, mux, and demux test modes across all lanes. Diodes specifies it for initialization-time configuration only - not runtime switching - due to potential signal disruption and metastability risks. The datasheet explicitly warns against dynamic toggling during active data transmission.
Does PI2EQX5904NJEX support PCIe 3.0 data rates?
No - PI2EQX5904NJEX is specified and characterized exclusively for PCIe 2.0 (5.0 Gbps) operation. Its equalization and de-emphasis ranges, jitter performance, and eye diagram compliance are validated only up to 2.5 GHz fundamental frequency. For PCIe 3.0, Diodes recommends PI3EQX8904 as the designated successor.
PI2EQX5904NJEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- PCI Express®(PCIe), ReDriver™
- Package/Case:
- 100-LBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Buffer, ReDriver
- Applications:
- PCIe
- Input:
- CML
- Output:
- CML
- Data Rate (Max):
- 5Gbps
- Number of Channels:
- 8
- Delay Time:
- 750ps
- Signal Conditioning:
- Input Equalization, Output De-Emphasis
- Capacitance - Input:
- -
- Voltage - Supply:
- 1.2V
- Current - Supply:
- 800mA
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 100-LBGA (11x11)
PI2EQX5904NJEX FAQ
1.How can I place an order for PI2EQX5904NJEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PI2EQX5904NJEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI2EQX5904NJEX reliable?
The price and inventory of PI2EQX5904NJEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI2EQX5904NJEX is usually 5 days.
3.What payment methods are accepted for PI2EQX5904NJEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI2EQX5904NJEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI2EQX5904NJEX?
PI2EQX5904NJEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI2EQX5904NJEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI2EQX5904NJEX?
For technical support, including PI2EQX5904NJEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI2EQX5904NJEX requirements.
6.How does Aetrix verify that PI2EQX5904NJEX is sourced from the original manufacturer or authorized distributors?
All PI2EQX5904NJEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI2EQX5904NJEX meets industry standards.
7.What is the process for return or replacement of PI2EQX5904NJEX?
All PI2EQX5904NJEX units undergo pre-shipment inspection (PSI). If there is an issue with PI2EQX5904NJEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI2EQX5904NJEX part is unused and in its original packaging.
Return procedure for PI2EQX5904NJEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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