Diodes Incorporated PI3V713-AZLEX

Overview

PI3V713-AZLEX from Pericom Semiconductor is a 3.3V, 7-channel analog video switch designed for VGA signal routing between dual ports (e.g., notebook and dock). It supports RGBHV + DDC (SDA/SCL) paths, delivers ±24mA H/V output drive, features 1.7GHz –3dB bandwidth, 4.8Ω typical on-resistance, and integrated 12kV HBM ESD protection on video I/O pins.

For engineers reviewing the PI3V713-AZLEX datasheet, PI3V713-AZLEX pinout, PI3V713-AZLEX application, or PI3V713-AZLEX equivalent, key selection criteria include dual-port VGA switching capability, 5V-to-3.3V DDC level shifting, low crosstalk (–38dB), flat on-resistance (0.5Ω), and TQFN-32 package compatibility with high-density PCB layouts.

Technical Context

This device implements a bidirectional analog multiplexer/demultiplexer architecture with independent control of RGBHV and DDC channels via a single SEL pin. The H/V outputs are actively buffered with rail-to-rail swing and ±24mA drive strength, while DDC paths operate as unidirectional 5V-to-3.3V level shifters using internal clamping diodes and pull-up structures.

Signal integrity is maintained through low parasitic capacitance (5.6pF ON-state), minimal insertion loss (–1.77dB at 10MHz), and tight channel matching (∆RON ≤ 0.1Ω). The 32-pin TQFN package enables compact placement near VGA connectors without compromising thermal performance under 500µA quiescent current.

Key Specifications

Pinout & Package

Package: 32-pin Thin Quad Flat No-Lead (TQFN), Pb-free and RoHS-compliant (ZLE code), 5mm × 5mm body, 0.5mm pitch, exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar analog video switching applications.

Compared with TS3V712EYZR and PI3USB31532ZLEX, the PI3V713-AZLEX uniquely combines full 7-channel VGA signal handling, active H/V buffering, and native 5V-to-3.3V DDC translation in a single TQFN package-enabling simpler, more reliable analog video routing in space-constrained docking solutions.

Availability

PI3V713-AZLEX is available at Aetrix Electronics and suitable for laptop docking stations, VGA KVM switches, legacy display adapters, and analog video signal integrity boosters requiring stable component supply and long-term obsolescence management.

Supply support for PI3V713-AZLEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-speed interface and signal integrity solutions, acquired by Diodes Incorporated in 2016; its legacy analog switch portfolio remains widely deployed in industrial and computing infrastructure.

The PI3V713-AZLEX belongs to Pericom's analog video switch product line, engineered specifically for high-fidelity VGA signal routing in portable computing and docking applications where ESD resilience and channel matching are critical.

FAQ

What is the maximum recommended trace length between PI3V713-AZLEX and VGA connector?

Based on measured 1.7GHz bandwidth and <–2.09dB insertion loss at 300MHz, the device supports up to 15cm of FR4 trace (50Ω controlled impedance) before requiring additional equalization. Layout best practices require ground vias every 5mm along RGBHV lines and separate 3.3V/5V power planes with 100nF + 10µF local decoupling at each VDD pin.

Can PI3V713-AZLEX operate with only 3.3V supply, or is 5V VDD mandatory?

The 5V VDD (Pin 16) is mandatory for DDC level-shifting functionality; omitting it disables SDA/SCL translation and may cause EDID communication failure. The 3.3V rails (Pins 4, 23, 32) power logic and analog switches. Both supplies must be present for full specification compliance.

How does the TEST pin affect normal operation if left unconnected?

Pin 29 (TEST) has an internal 100kΩ pull-up resistor; leaving it unconnected places it at logic HIGH, disabling test mode and enabling standard SEL-controlled switching. No external biasing is required for default operation, but grounding it during production testing activates diagnostic functions.

Is there any restriction on SEL signal slew rate or voltage threshold?

The SEL pin accepts 0V to 3.6V logic levels regardless of VDD; VIH is guaranteed ≥2V and VIL ≤0.8V. No minimum slew rate is specified, but transitions slower than 100ns may increase propagation delay uncertainty. For deterministic switching, maintain >1V/ns edge rate with series termination if driving from high-impedance sources.