Diodes Incorporated PI3WVR628XBEX

Overview

PI3WVR628XBEX from Diodes Incorporated is a 3-lane, 2:1 MIPI switch supporting both D-PHY (up to 4.5 Gb/s) and C-PHY (up to 3.5 Gsps) protocols, with 6.0 GHz typical bandwidth, −30 dB crosstalk at 2.25 GHz, and 5.0 Ω typical R_ON for HS/LP MIPI switching. It serves as a dual-data-lane signal router in camera/display interface paths of mobile devices.

For engineers reviewing the PI3WVR628XBEX datasheet, PI3WVR628XBEX pinout, PI3WVR628XBEX application, or PI3WVR628XBEX equivalent, key selection criteria include differential skew (2 ps typical), R_ON flatness (0.3 Ω), supply range (1.5–3.6 V), and X1-LGA2417-24 package compatibility with high-density MIPI routing constraints.

Technical Context

This device implements a 6-channel SPDT architecture optimized for MIPI CSI/DSI signal routing between two sources (Port A and Port B) and one common output (COM), supporting simultaneous clock and data lane switching under synchronous SEL/OE control logic. It maintains signal integrity across both LP (0–1.3 V) and HS (0–0.5 V) MIPI voltage domains.

The switch features break-before-make timing (450 ns), low propagation delay (0.25 ns), and matched on-resistance (∆R_ON = 0.1 Ω) to minimize inter-lane skew-critical for C-PHY trio alignment and D-PHY byte clock recovery in multi-camera modules.

Key Specifications

Pinout & Package

PI3WVR628XBEX uses a 24-pin X1-LGA2417-24 package (1.7 mm × 2.4 mm, 0.4 mm pitch), designed for ultra-compact placement in space-constrained mobile PCBs. The land grid array eliminates solder joint reliability concerns associated with fine-pitch QFN leads while enabling direct ground plane coupling via bottom thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar MIPI 2:1 switch applications.

Compared with TS3DV642RHBR and PI3WVR648XBEX, PI3WVR628XBEX uniquely balances dual-lane C-PHY/D-PHY flexibility, ultra-low R_ON flatness, and minimal 1.5–3.6 V supply dependency-making it optimal for cost-sensitive, space-constrained dual-camera mobile designs requiring protocol agility.

Availability

PI3WVR628XBEX is available at Aetrix Electronics and suitable for smartphone camera modules, tablet display interfaces, and laptop embedded vision systems requiring stable component supply and qualified automotive-grade variants.

Supply support for PI3WVR628XBEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog and mixed-signal solutions for consumer, computing, and industrial markets.

The PI3WVR628XBEX belongs to Diodes' Pericom MIPI switch product line, engineered specifically for high-fidelity, low-skew signal routing in mobile imaging and display subsystems where protocol flexibility and PCB space efficiency are critical.

FAQ

What is the maximum supported C-PHY data rate for PI3WVR628XBEX?

The PI3WVR628XBEX supports up to 3.5 Gsps in C-PHY mode, validated per JEDEC JESD220 specification for MIPI C-PHY v1.2. This enables transmission of 12-bit pixel data at 280 MHz lane rate across all three phases of a C-PHY trio, sufficient for 4K@30fps camera sensor interfaces.

Does PI3WVR628XBEX require external termination resistors?

No. The PI3WVR628XBEX integrates on-die 100 Ω differential termination for all MIPI I/O ports, eliminating need for external resistors. This reduces PCB area, improves impedance matching consistency, and avoids layout-induced skew from discrete termination placement mismatches.

Can PI3WVR628XBEX operate with 1.8 V VDD only?

Yes. The device operates across 1.5 V to 3.6 V, and 1.8 V is a fully supported nominal supply voltage. At 1.8 V, R_ON remains 5.0 Ω typical, ∆R_ON stays ≤0.1 Ω, and AC performance-including 6.0 GHz bandwidth and −30 dB crosstalk-is maintained per DS42007 Rev 4-2 characterization data.

How does the OE pin behave during power-up sequencing?

The OE pin defaults to high-impedance until VDD reaches 1.0 V, after which internal power-on reset holds OE inactive (high) until VDD stabilizes. This ensures all I/Os remain in Hi-Z state during power ramp, preventing bus contention or false switching during system boot sequences.