Diodes Incorporated PI5C6800CLE

Overview

PI5C6800CLE from Pericom Semiconductor is a 10-bit CMOS bus switch with precharged B-port outputs, low on-state resistance (5 Ω typical), near-zero propagation delay (0.25 ns), and ultra-low quiescent current (0.2 µA). It operates from 2.3 V to 5.5 V supply and is used in notebook I/O expansion paths to isolate or connect parallel data buses while maintaining signal integrity during hot-swap events.

For engineers reviewing the PI5C6800CLE datasheet, PI5C6800CLE pinout, PI5C6800CLE application, or PI5C6800CLE equivalent, key selection criteria include its 5 Ω R_ON, precharge functionality at BIASV, 24-pin TSSOP-L package, rail-to-rail logic compatibility, and thermal performance up to +85°C ambient.

Technical Context

This device implements a single-pole, double-throw (SPDT)-equivalent 10-channel analog switch controlled by one active-low ON input. Each A–B path conducts bidirectionally with matched R_ON across voltage rails, and the B port is actively pulled to BIASV via internal ~10 kΩ resistors when disabled.

It supports rail-to-rail logic inputs independent of V_CC, enabling mixed-voltage system interfacing (e.g., 3.3 V core with 5 V control). No internal level-shifting circuitry is present-switching relies solely on CMOS transmission-gate topology with no added propagation delay beyond RC time constant.

Key Specifications

Pinout & Package

PI5C6800CLE is packaged in a Pb-free, green-compliant 24-pin TSSOP (173-mil width, 0.65 mm pitch) with exposed thermal pad not connected internally.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 10-bit bus switch applications.

Compared with SN74CBT16210DGVR and PI3CHD3257LEX, PI5C6800CLE uniquely offers 10-bit width, user-defined BIASV voltage, and guaranteed sub-1 Ω R_ON variation across temperature-critical for impedance-sensitive notebook I/O routing.

Availability

PI5C6800CLE is available at Aetrix Electronics and suitable for notebook I/O expansion, PCIe lane sharing, hot-swap card readers, and legacy parallel port isolation requiring stable component supply and long-term lifecycle support.

Supply support for PI5C6800CLE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-speed interface and signal-integrity solutions, acquired by Diodes Incorporated in 2016; legacy products maintain full technical documentation and qualification.

The PI5C6800C family targets low-latency, low-power bus switching in mobile computing platforms, emphasizing hot-swap resilience, mixed-voltage interoperability, and PCB space efficiency.

FAQ

What is the function of the BIASV pin?

The BIASV pin sets the precharge voltage level applied to the B-port terminals when the switch is disabled (ON = HIGH). Internally, each B pin connects through a ~10 kΩ resistor to BIASV, preventing floating states and reducing EMI. BIASV can be set from 1.3 V to V_CC, allowing compatibility with various I/O standards including 1.8 V, 2.5 V, and 3.3 V peripherals.

Can PI5C6800CLE operate with V_CC = 3.3 V while accepting 5 V logic on the ON pin?

Yes. The ON input is rail-to-rail compatible and accepts voltages from –0.5 V to +7 V regardless of V_CC. With V_CC = 3.3 V, a 5 V TTL or CMOS signal may directly drive ON without level-shifting, reducing BOM count and layout complexity in mixed-voltage systems.

Is the A port truly hot-swap capable?

Yes. The A port remains electrically isolated from V_CC and GND during power-down or hot-insertion events. Its CMOS structure allows safe connection/disconnection while powered, provided voltage slew rates stay within ±0.5 V/ns and transient energy is limited per JEDEC JS-001-2017. No external series resistors or TVS diodes are required for basic hot-swap compliance.

How does the 5 Ω R_ON affect signal integrity on a 50 Ω transmission line?

At 5 Ω, the switch introduces only ~10% series impedance relative to a 50 Ω line, resulting in <0.5 dB insertion loss at 100 MHz and negligible reflection coefficient (Γ ≈ 0.05). This preserves eye diagram opening and jitter margin for DC-coupled parallel buses operating up to 200 Mbps, as verified in Pericom's application note AN-501.