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Diodes Incorporated PI6C10806BLEX
- Part No.:
- PI6C10806BLEX
- Manufacturer:
- Diodes Incorporated
- Category:
- Clock Buffers, Drivers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
PI6C10806BLEX.pdf
- Description:
- IC CLK BUFFER 1:6 160MHZ 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,529
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Product details
Overview
PI6C10806BLEX from Diodes Incorporated is a low-skew, 1:6 LVCMOS clock buffer with crystal oscillator input interface (10–50 MHz), dual independent output enables (ENABLE1/ENABLE2), six LVCMOS outputs (BCLK0–BCLK5), and support for 1.5V/1.8V/2.5V/3.3V core/output supply rails. It delivers ≤80 ps output-to-output skew and operates up to 160 MHz when driven by an external clock source - deployed in high-speed networking timing distribution.
For engineers reviewing the PI6C10806BLEX datasheet, PI6C10806BLEX pinout, PI6C10806BLEX application, or PI6C10806BLEX equivalent, key selection criteria include multi-voltage operation, synchronous enable control per output group, sub-100 ps skew performance, and crystal-input compatibility for jitter-sensitive clock trees.
Technical Context
The PI6C10806BLEX integrates a crystal oscillator driver stage followed by a low-skew fanout buffer with two independently enabled output groups: BCLK[0:4] (five outputs) and BCLK5 (single output). Input accepts either a parallel-mode fundamental crystal (10–50 MHz, CL = 18 pF) or an external LVCMOS clock signal up to 160 MHz.
It supports split-rail operation: VDD (core logic) and VDDO (output drivers) are independently configurable across 1.5V, 1.8V, 2.5V, or 3.3V. Output rise/fall times remain ≤800 ps down to 1.8V, and RMS phase jitter is as low as 0.098 ps (typical, 100 Hz–1 MHz, 3.3V operation).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & grouping | 6 LVCMOS outputs: five in BCLK[0:4], one dedicated BCLK5 - each group has independent enable control |
| Input interface | XTAL_IN/XTAL_OUT pins support parallel-resonant crystal (10–50 MHz) or external clock up to 160 MHz |
| Output skew | ≤80 ps max between any two outputs - ensures tight timing alignment in multi-lane interfaces |
| Supply flexibility | VDD (core) and VDDO (outputs) independently set to 1.5V/1.8V/2.5V/3.3V - enables mixed-voltage system integration |
| RMS phase jitter | 0.098 ps (typical, 100 Hz–1 MHz, 25 MHz @ 3.3V) - meets stringent jitter budgets for SerDes clocking |
| Enable timing | Output enable/disable latency ≤4 clock cycles - supports dynamic clock gating without metastability risk |
| Operating temperature | –40°C to +85°C industrial range - validated for sustained operation in telecom and industrial edge equipment |
Pinout & Package
Package: 16-pin, 173-mil wide TSSOP (L), RoHS-compliant, halogen- and antimony-free "Green" construction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (XTAL_OUT) | Crytal oscillator output | Drives crystal's parallel-resonant mode; requires external load capacitors (e.g., C1=C2=15 pF for CL=18 pF) |
| 2 (ENABLE2) | Active-high enable for BCLK5 | Controls single-output group; synchronous assertion avoids glitch generation on BCLK5 |
| 3 (GND) | Analog/digital ground reference | Common return for core logic, outputs, and crystal circuit - must be low-impedance plane |
| 4 (BCLK0) | LVCMOS clock output | Member of five-output group (BCLK[0:4]); shares ENABLE1 control and VDDO rail |
| 5 (VDDO) | Output driver power supply | Independent voltage rail for all six outputs - sets logic threshold and drive strength |
| 6 (BCLK1) | LVCMOS clock output | Member of five-output group (BCLK[0:4]); matched routing critical for skew control |
| 7 (GND) | Ground | Second GND pin - decouples output switching noise from core logic |
| 8 (BCLK2) | LVCMOS clock output | Center output in BCLK[0:4] group - used for length-matching reference in PCB layout |
| 9 (VDD) | Core logic power supply | Supplies internal oscillator, control logic, and input buffers - may differ from VDDO |
| 10 (BCLK3) | LVCMOS clock output | Member of five-output group; routed with controlled impedance (50 Ω to VDDO/2) |
| 11 (GND) | Ground | Third GND pin - supports clean return path for high-frequency output transitions |
| 12 (VDDO) | Output driver power supply | Duplicate VDDO pin - reduces IR drop and improves PSRR for output stage |
| 13 (VDDO) | Output driver power supply | Third VDDO pin - enhances current delivery to all six outputs under simultaneous switching |
| 14 (BCLK4) | LVCMOS clock output | Fifth and final output in BCLK[0:4] group - enables full 1:5 fanout with shared enable |
| 15 (ENABLE1) | Active-high enable for BCLK[0:4] | Controls five-output group synchronously; assertion aligns with clock edge to prevent runt pulses |
| 16 (XTAL_IN) | Crytal oscillator input | Accepts crystal feedback or external clock; overdrive-tolerant for non-crystal sources |
Key Features
| Feature | Design Value |
|---|---|
| Six low-skew LVCMOS outputs | ≤80 ps output-to-output skew ensures deterministic timing across multi-lane PHYs and memory interfaces |
| Dual independent output enables | ENABLE1 controls BCLK[0:4]; ENABLE2 controls BCLK5 - enables selective clock gating per subsystem |
| Crystal + external clock input support | XTAL_IN/XTAL_OUT interface accepts 10–50 MHz crystals or up to 160 MHz LVCMOS clock - simplifies design reuse |
| Multi-voltage operation | VDD and VDDO independently configurable at 1.5V/1.8V/2.5V/3.3V - matches diverse SoC I/O standards |
| Low-jitter performance | 0.098 ps typical RMS phase jitter (100 Hz–1 MHz, 25 MHz @ 3.3V) - suitable for 10G+ serial link reference clocks |
| Industrial temperature range | Validated operation from –40°C to +85°C - supports deployment in uncontrolled ambient environments |
Applications
| 10G Ethernet Switch Timing | PCIe Gen3/Gen4 Reference Clock Distribution |
|---|---|
|
Use Scenario: Distributing a low-jitter 156.25 MHz reference clock to multiple MAC/PHY devices in a layer-3 switch chassis. IC Role / Device Role / Timing Role: Crystal-to-LVCMOS clock buffer providing six synchronized outputs with independent enables for port-level clock gating. Use Value: ≤80 ps skew ensures setup/hold margin compliance across 10GBase-KR lanes; dual enables reduce dynamic power by 42% during port sleep states. |
Use Scenario: Fanout of a 100 MHz PCIe reference clock to root complex, endpoint, and switch ICs in a server motherboard. IC Role / Device Role / Timing Role: Low-jitter 1:6 buffer with split VDD/VDDO rails matching host CPU (1.8V) and add-in cards (3.3V). Use Value: 0.098 ps RMS jitter meets PCIe Gen4 spec (≤0.15 ps); independent enables allow hot-plug clock management without affecting active links. |
| Industrial PLC Backplane Clocking | 5G Small Cell Baseband Timing |
|
Use Scenario: Delivering synchronized 25 MHz clocks to multiple FPGA-based I/O modules across a ruggedized backplane. IC Role / Device Role / Timing Role: Industrial-grade clock buffer with –40°C to +85°C operation and crystal input for self-contained timing. Use Value: Crystal interface eliminates need for external oscillator; 1.5V/1.8V support enables direct interfacing with low-power FPGAs and ADCs. |
Use Scenario: Generating six phase-aligned clocks for RF transceivers, digital front-end FPGAs, and ADC/DACs in compact 5G mmWave units. IC Role / Device Role / Timing Role: High-frequency (up to 160 MHz) LVCMOS buffer with ultra-low jitter for baseband sampling clock distribution. Use Value: 160 MHz capability supports 122.88 MHz and 153.6 MHz 5G NR sampling clocks; ≤80 ps skew maintains EVM < 2.5% across RF chains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT PI6C20400 | 4-output, no crystal input, fixed 3.3V-only supply, 100 ps skew | Lacks crystal interface and dual-enable architecture; limited to simpler fanout roles | Select only if system already uses external oscillator and requires minimal pin count |
| ON Semi NB3N502M | 2-output, integrated crystal oscillator (XO), 3.3V-only, 150 ps skew | Self-contained XO eliminates external crystal but offers fewer outputs and higher jitter (0.35 ps) | Choose when board space is constrained and 2-output fanout suffices with built-in oscillator |
Compared with IDT PI6C20400 and ON Semi NB3N502M, the PI6C10806BLEX uniquely combines crystal input, six outputs with grouped enables, multi-voltage support, and sub-100 ps skew - making it the only option for scalable, low-jitter, crystal-referenced timing in dense networking and 5G infrastructure.
Availability
PI6C10806BLEX is available at Aetrix Electronics and suitable for 10G Ethernet switch timing, PCIe Gen4 reference clock distribution, and industrial PLC backplane clocking requiring stable component supply across extended product lifecycles.
Supply support for PI6C10806BLEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.
The PI6C10806BLEX belongs to Diodes' PI6C clock buffer product line, engineered for low-skew, multi-voltage clock distribution in high-speed digital systems where jitter, power, and layout flexibility are critical.
FAQ
What crystal specifications are required for PI6C10806BLEX?
The PI6C10806BLEX requires a fundamental-mode parallel-resonant crystal with frequency 10–50 MHz, load capacitance 18 pF, ESR ≤50 Ω, and drive level ≤1 mW. Recommended external load capacitors are C1 = C2 = 15 pF for CL = 18 pF crystals. The device does not support series-mode or overtone crystals.
Can PI6C10806BLEX operate with different voltages on VDD and VDDO?
Yes - VDD (core logic) and VDDO (output drivers) are fully independent. Valid combinations include 1.8V VDD with 3.3V VDDO for interfacing with mixed-voltage SoCs, or 1.5V VDD with 2.5V VDDO to optimize power vs. drive strength. Each rail must be within its specified tolerance (±5% for 1.5V/2.5V/3.3V, ±0.2V for 1.8V).
How does the dual-enable architecture improve system power management?
ENABLE1 controls BCLK[0:4] and ENABLE2 controls BCLK5 independently, allowing selective clock gating per functional block. For example, in a switch ASIC, BCLK[0:4] can serve active ports while BCLK5 clocks a standby management controller - reducing dynamic power by disabling unused clock domains without software intervention.
Is PI6C10806BLEX qualified for automotive applications?
No - the PI6C10806BLEX is specified for industrial temperature range (–40°C to +85°C) and is not AEC-Q100 qualified. Diodes offers automotive-qualified alternatives (e.g., PI6C10806BQ) with PPAP support, IATF 16949 manufacturing, and extended temperature validation; contact Diodes directly for those variants.
PI6C10806BLEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Fanout Buffer (Distribution)
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:6
- Differential - Input:Output:
- No/No
- Input:
- Crystal
- Output:
- LVCMOS
- Frequency - Max:
- 160 MHz
- Voltage - Supply:
- 1.425V ~ 3.465V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-TSSOP
PI6C10806BLEX FAQ
1.How can I place an order for PI6C10806BLEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6C10806BLEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6C10806BLEX reliable?
The price and inventory of PI6C10806BLEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6C10806BLEX is usually 5 days.
3.What payment methods are accepted for PI6C10806BLEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6C10806BLEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6C10806BLEX?
PI6C10806BLEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6C10806BLEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6C10806BLEX?
For technical support, including PI6C10806BLEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6C10806BLEX requirements.
6.How does Aetrix verify that PI6C10806BLEX is sourced from the original manufacturer or authorized distributors?
All PI6C10806BLEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6C10806BLEX meets industry standards.
7.What is the process for return or replacement of PI6C10806BLEX?
All PI6C10806BLEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6C10806BLEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6C10806BLEX part is unused and in its original packaging.
Return procedure for PI6C10806BLEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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