Diodes Incorporated PI6C20400AHE

Overview

PI6C20400AHE from Diodes Incorporated is a PCIe® 2.0-compliant 1:4 differential clock driver IC designed as a companion to the PI6C410BS clock synthesizer. It distributes HCSL SRC input across four differential output pairs (OUT0–OUT3) with selectable PLL or bypass mode, <50 ps cycle-to-cycle jitter, <1 ps additive RMS phase jitter, and 3.3V operation - deployed in server motherboard clock trees for Intel PCIe chipsets.

For engineers reviewing the PI6C20400AHE datasheet, PI6C20400AHE pinout, PI6C20400AHE application, or PI6C20400AHE equivalent, key selection criteria include PCIe 2.0 timing compliance, SMBus-programmable PLL bandwidth, tristate control per output pair via OE_0/OE_3, and dual power domains (VDD/VDD_A) for optimized noise isolation in high-speed digital systems.

Technical Context

The PI6C20400AHE implements a current-mode HCSL output buffer with programmable IREF-based output current (nominal 2.32 mA × 6 = 13.9 mA), supporting both DC-coupled (50 Ω to ground) and AC-coupled (with external 350 mV bias) termination. Its dual-supply architecture separates PLL core (VDD_A) and I/O (VDD) domains to suppress supply-induced jitter.

It operates in two functional modes: PLL mode (100 MHz input, low-jitter regeneration) and bypass mode (100–400 MHz input pass-through). Mode selection is controlled by the PLL/BYPASS# pin, while PLL bandwidth (high/low) is set via PLL_BW#, and output enable/disable is managed per pair through OE_0/OE_3 and globally via SRC_STOP#/PWRDWN#.

Key Specifications

Pinout & Package

PI6C20400AHE is packaged in a 28-pin SSOP (H28), 209-mil wide, RoHS- and halogen-free "Green" package with exposed pad not present. Pin functions are validated per Diodes DS43442 Rev 2-2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 2.0 clock fanout applications.

Compared with IDT 8T49N241 and ON Semi NB3N551, the PI6C20400AHE uniquely balances PCIe 2.0 jitter performance, per-pair enable control, and compact SSOP packaging - making it optimal for space-constrained server boards requiring precise, configurable clock distribution without over-spec'ing for PCIe 3.0.

Availability

PI6C20400AHE is available at Aetrix Electronics and suitable for PCIe 2.0 server motherboards, Intel chipset timing subsystems, and industrial embedded backplanes requiring stable component supply, long-term lifecycle assurance, and RoHS 3/Green compliance.

Supply support for PI6C20400AHE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, industrial, and communications markets.

The PI6C20400AHE belongs to Diodes' Pericom timing product line, engineered specifically for PCIe 2.0-compliant clock distribution in Intel-platform servers and workstations - emphasizing low jitter, flexible control, and robust signal integrity in thermally dense environments.

FAQ

What is the function of the IREF pin, and how is its value determined?

The IREF pin sets the output current for all HCSL output pairs via an external precision resistor. With RREF = 475 Ω (1%), the device draws 2.32 mA reference current, resulting in 13.9 mA per output pair (6× IREF). This value ensures correct 0.7 V swing into 50 Ω loads and is validated per DS43442 Figure 3 and Table 7.

Can PI6C20400AHE operate in PCIe 3.0 systems?

No - the PI6C20400AHE is specified and characterized only for PCIe 2.0 compliance (5 GT/s). Its maximum bypass-mode input frequency is 400 MHz, and additive jitter performance is guaranteed only under PCIe 2.0 filter conditions. For PCIe 3.0, Diodes recommends the PI6C410BS+PI6C20400AHE combination is not sufficient; use PI6C41012 or IDT 8T49N241 instead.

How does OE_INV affect SRC_STOP# and PWRDWN# behavior?

When OE_INV = HIGH (3.3 V), the logic polarity of OE_0, OE_3, SRC_STOP#, and PWRDWN# is inverted: OE_0/OE_3 become active-low, and SRC_STOP#/PWRDWN# become active-high. This allows direct interfacing with control buses that drive inverted enable signals, without external logic gates - confirmed in Pin Descriptions section of DS43442.

Is AC-coupled operation supported, and what external components are required?

Yes - AC-coupled operation is supported but requires external DC biasing of the receiver side to ~350 mV, because the PI6C20400AHE provides no internal bias. A typical implementation uses 0.1 µF series capacitors plus a Thevenin divider (e.g., 10 kΩ to VDD, 10 kΩ to GND) at the receiver input. This is explicitly detailed in Application Information section (page 11) of DS43442.