Diodes Incorporated PI6C20400ALE

Overview

PI6C20400ALE from Pericom Semiconductor is a PCIe® 2.0-compliant differential clock buffer that distributes one differential SRC clock input to four differential output pairs, supporting both PLL (100 MHz) and bypass (100–400 MHz) modes. It features <1 ps additive RMS phase jitter, <50 ps cycle-to-cycle jitter, low skew (<50 ps), SMBus-controlled tristate outputs, and programmable PLL bandwidth. Used in Intel PCIe chipset companion clock distribution.

For engineers reviewing the PI6C20400ALE datasheet, PI6C20400ALE pinout, PI6C20400ALE application, or PI6C20400ALE equivalent, key selection criteria include PCIe 2.0 phase jitter compliance, differential output current control via IREF, dual-mode operation (PLL/BYPASS#), SMBus register access for output enable/inversion, and 28-pin TSSOP (L28) packaging with 3.3V supply.

Technical Context

The PI6C20400ALE implements a current-mode differential output stage with externally set output current (IREF = 2.32 mA, RREF = 475 Ω), delivering 0.7 V differential swing into 100 Ω loads. Its PLL supports 100 MHz operation with selectable bandwidth (high/low), while bypass mode enables wideband fanout from 100 MHz to 400 MHz.

Control logic integrates three independent enable paths: dedicated OE_0/OE_3 pins, global SRC_STOP#/PWRDWN# with OE_INV inversion option, and SMBus-configurable output enable/disable per channel. All outputs enter high-impedance state when PWRDWN# is asserted, with <300 µs drive disable timing and <1 ms stabilization on de-assertion.

Key Specifications

Pinout & Package

Package: 28-pin TSSOP (L28), 173-mil wide, Pb-free and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N502, the PI6C20400ALE uniquely combines PCIe 2.0-compliant jitter performance, hardware-selectable PLL/bypass operation, and SMBus-configurable per-output control-making it optimal for Intel chipset-based systems requiring both flexibility and deterministic timing.

Availability

PI6C20400ALE is available at Aetrix Electronics and suitable for PCIe root complex clock distribution, server backplane timing hubs, embedded storage controller timing, and industrial PCIe-based data acquisition requiring stable component supply and long-term lifecycle support.

Supply support for PI6C20400ALE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-performance timing, interface, and signal integrity solutions, acquired by Diodes Incorporated in 2016; its clock products remain widely deployed in enterprise and industrial platforms.

The PI6C20400A series targets PCIe 2.0 clock distribution architectures, specifically designed as a companion device to Pericom's PI6C410BS clock synthesizer for Intel chipset platforms.

FAQ

What is the function of the IREF pin, and how is it configured?

The IREF pin sets the differential output current using an external 475 Ω ±1% resistor connected to VDD. This establishes a nominal 2.32 mA reference current, which scales output drive strength to deliver 0.7 V differential swing into 100 Ω loads. The resistor must be placed close to the pin with minimal trace length to maintain accuracy and noise immunity.

How does the PLL/BYPASS# pin affect clock distribution behavior?

When PLL/BYPASS# is high, the device operates in bypass mode, passing the SRC input directly to outputs across 100–400 MHz. When low, it engages the internal PLL locked to 100 MHz, filtering input jitter and providing frequency-stable outputs. This pin enables hardware-selectable trade-offs between bandwidth and jitter cleanup without firmware involvement.

Can all four output pairs be independently enabled or disabled?

Yes - OE_0 and OE_3 provide hardware enable control for OUT0/OUT0# and OUT3/OUT3#. Additionally, SMBus registers (Data Byte 1, bits 1,2,5,6) allow per-output enable/disable of all four pairs. This dual-layer control supports both board-level design flexibility and runtime power management in host firmware.

What happens to outputs during PWRDWN# assertion, and what is the recovery timing?

Asserting PWRDWN# forces all outputs to high-impedance within <300 µs and reduces supply current to ≤40 mA (driven outputs) or ≤12 mA (tristated). Upon de-assertion, outputs stabilize within <1 ms. During this state, SCLK and SDA must be tri-stated to prevent bus contention, as the device acts as an SMBus slave only when powered.