Diodes Incorporated PI6C20400BHEX

Overview

PI6C20400BHEX from Diodes Incorporated is a PCIe 3.0-compliant differential clock buffer with four pairs of low-noise, low-skew outputs (≤50 ps skew, ≤50 ps cycle-to-cycle jitter), programmable PLL bandwidth, and SMBus-controlled tristate enable. It operates at 3.3 V, supports 100–400 MHz bypass mode or 100 MHz PLL mode, and serves as a companion to PCIe clock generators in server motherboard timing trees.

For engineers reviewing the PI6C20400BHEX datasheet, PI6C20400BHEX pinout, PI6C20400BHEX application, or PI6C20400BHEX equivalent, key selection criteria include additive phase jitter (<1 ps RMS), differential output current control via IREF, SMBus-configurable output enable per channel, and dual power domains (VDD_A/VSS_A for PLL, VDD/VSS for outputs).

Technical Context

The PI6C20400BHEX implements a dual-path architecture: one path routes the SRC/SRC# differential input directly to outputs in bypass mode (100–400 MHz), while the other passes through a configurable PLL (100 MHz fixed output) with selectable bandwidth (high/low via PLL_BW#). Output states are controlled independently by OE_0/OE_3 and globally by SRC_STOP# and PWRDWN#, with tristate behavior enforced when either is asserted.

It integrates an SMBus slave interface (7-bit address 0x6E) supporting indexed block read/write for register-level control of output enable, PLL/bypass selection, SRC_STOP# response, and PLL bandwidth. The device uses current-mode differential outputs with external IREF resistor (475 Ω) setting nominal output current (13.9 mA typical), delivering 0.7 V differential swing into 100 Ω loads.

Key Specifications

Pinout & Package

PI6C20400BHEX is packaged in a 28-pin SSOP (H28), 209-mil wide, lead-free and RoHS-compliant package with exposed thermal pad not connected internally.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8P34S1208NLGI and Microchip SY89322LMG, the PI6C20400BHEX uniquely combines PCIe 3.0 additive jitter compliance (<1 ps RMS), SMBus-configurable per-output control, and dual-mode (PLL/bypass) operation - making it optimal for dynamic, multi-slot server and storage platforms requiring runtime clock management.

Availability

PI6C20400BHEX is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch timing, enterprise SSD controller clocking, and AI accelerator board development requiring stable component supply and long-term lifecycle support.

Supply support for PI6C20400BHEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6C20400BHEX belongs to Diodes' Pericom timing product line, engineered specifically for PCIe 3.0 infrastructure applications requiring ultra-low additive jitter, flexible output control, and robust signal integrity in dense server and storage PCB layouts.

FAQ

What is the function of the IREF pin on PI6C20400BHEX?

The IREF pin connects to an external 475 Ω ±1% resistor to set the nominal differential output current at 13.9 mA. This current determines the 0.7 V differential swing into a 100 Ω load and directly impacts output rise/fall times and jitter performance. Deviation beyond ±12% tolerance alters output amplitude and may violate PCIe 3.0 voltage specifications.

How does the PLL/BYPASS# pin affect clock output behavior?

When PLL/BYPASS# is low, the device operates in bypass mode: SRC/SRC# is routed directly to all four output pairs, supporting 100–400 MHz input frequencies. When high, the internal PLL locks to SRC/SRC# and generates a clean 100 MHz output, filtering input jitter. Mode selection is latched on power-up and can be overridden via SMBus register bit 1.

Can PI6C20400BHEX drive HCSL or LVDS loads directly?

No - PI6C20400BHEX outputs are current-mode 0.7 V differential drivers optimized for 100 Ω termination. They meet PCIe 3.0 AC-coupled differential signaling specs but lack internal termination or level-shifting for direct HCSL (800 mV) or LVDS (350 mV) compliance. External resistive networks or level translators are required for non-PCIe signaling standards.

What happens to outputs when both SRC_STOP# and PWRDWN# are asserted?

Both signals force all eight output terminals (OUT0–OUT3 and their complements) into high-impedance tristate. PWRDWN# takes precedence: when asserted, SCLK and SDA must also be tristated to avoid bus contention. The device draws only 12 µA in this state, and outputs recover within 1 ms after de-assertion per Figure 2 in DS43443 Rev 1-2.