Diodes Incorporated PI6C20400BLE

Overview

PI6C20400BLE from Diodes Incorporated is a PCIe 3.0-compliant 1:4 differential clock buffer with PLL/bypass mode selection, <50 ps cycle-to-cycle jitter, <1 ps additive RMS phase jitter, and 4 differential output pairs (OUT0–OUT3 with complementary # pins). It serves as a companion to PCIe 3.0 clock generators in high-speed server and storage motherboard timing trees.

For engineers reviewing the PI6C20400BLE datasheet, PI6C20400BLE pinout, PI6C20400BLE application, or PI6C20400BLE equivalent, key selection criteria include PCIe Gen3 additive jitter compliance, SMBus-controllable tristate outputs, programmable PLL bandwidth, and dual-package availability (28-pin TSSOP).

Technical Context

The PI6C20400BLE operates in two distinct clock distribution modes: PLL mode (100 MHz input, low-jitter regeneration) and bypass mode (100–400 MHz, minimal latency path). Its internal current-mode differential output buffers deliver 0.7 V swing into 100 Ω differential loads with ±12% current accuracy controlled via external IREF resistor.

Control logic integrates three independent enable paths: dedicated OE_0/OE_3 pins for per-output enable, SRC_STOP# and PWRDWN# for global tristate control, and SMBus register access for dynamic configuration of PLL bandwidth, output mode, and SRC_STOP# response behavior - all while maintaining PCIe 3.0 phase jitter filtering.

Key Specifications

Pinout & Package

PI6C20400BLE is packaged in a RoHS-compliant 28-pin TSSOP (L28, 173-mil wide) with exposed thermal pad (not electrically connected). Pin numbering follows standard counter-clockwise layout from notch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53302-A01, PI6C20400BLE offers optimal balance of PCIe 3.0 compliance, low-latency bypass mode, compact TSSOP packaging, and SMBus configurability - making it ideal for cost-sensitive, high-volume PCIe 3.0 fanout applications where source clock quality is assured.

Availability

PI6C20400BLE is available at Aetrix Electronics and suitable for enterprise SSD controllers, PCIe switch-based accelerator cards, and server motherboard clock trees requiring stable component supply and industrial temperature range support.

Supply support for PI6C20400BLE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6C20400BLE belongs to Diodes' PCIe timing portfolio, designed specifically to meet the stringent jitter, skew, and configurability requirements of PCIe 3.0 infrastructure - including servers, storage, and accelerators.

FAQ

What is the function of the IREF pin on PI6C20400BLE?

The IREF pin connects to an external 475 Ω ±1% resistor to set the internal current-source value (2.32 mA), which directly determines the differential output current (IOH = 6 × IREF = 13.9 mA). This ensures precise 0.7 V swing into 100 Ω differential loads without external termination, maintaining signal integrity across temperature and voltage variation.

Can PI6C20400BLE operate without an external clock generator?

No. PI6C20400BLE is a clock buffer-not a clock generator-and requires a differential SRC input (0.7 V) from a compliant PCIe clock synthesizer such as PI6C410. It lacks an internal oscillator or crystal interface and cannot generate clocks autonomously; its role is strictly fanout, conditioning, and distribution of an existing reference.

How does the PLL/BYPASS# pin affect timing performance?

When PLL/BYPASS# is low, the device operates in PLL mode (100 MHz only), regenerating the clock with ultra-low additive jitter (<1 ps RMS). When high, it enters bypass mode (100–400 MHz), passing the input clock with minimal latency and <50 ps cycle-to-cycle jitter-ideal for multi-rate systems where latency matters more than jitter cleaning.

Is PI6C20400BLE pin-compatible with PI6C20400BHE (SSOP package)?

Yes. PI6C20400BLE (TSSOP) and PI6C20400BHE (SSOP) share identical pinout, electrical characteristics, and functionality. The only difference is mechanical: L28 (173-mil wide TSSOP) vs. H28 (209-mil wide SSOP). Layouts can be reused with footprint adaptation; thermal and EMI performance differ slightly due to package geometry.