Diodes Incorporated PI6C20400BLEX

Overview

PI6C20400BLEX from Diodes Incorporated is a PCIe 3.0-compliant differential clock buffer with four pairs of low-jitter outputs, <1 ps additive RMS phase jitter, <50 ps cycle-to-cycle jitter, and programmable PLL bandwidth. It operates at 3.3 V and supports both PLL (100 MHz) and bypass (100–400 MHz) modes for Intel PCIe® 3.0 chipset timing distribution.

For engineers reviewing the PI6C20400BLEX datasheet, PI6C20400BLEX pinout, PI6C20400BLEX application, or PI6C20400BLEX equivalent, key selection considerations include PCIe Gen3 additive jitter compliance, SMBus-controlled tristate enable/disable per output pair, differential current-mode output drive (IREF-settable), and dual-supply isolation (VDD_A/VSS_A for PLL core).

Technical Context

The PI6C20400BLEX implements a configurable 1:4 fanout architecture with selectable PLL or bypass signal path. Its PLL supports 100 MHz operation with two programmable bandwidth settings (high/low), while bypass mode delivers input-to-output latency under 6.5 ns with <50 ps skew across all eight differential outputs.

It integrates SMBus slave interface (7-bit address 0x6E) for register-level control of output enables, SRC_STOP# behavior, PLL/BYPASS mode, and PLL bandwidth. All differential outputs are current-mode drivers with external IREF resistor (475 Ω typical) setting nominal 13.9 mA output current (6 × IREF).

Key Specifications

Pinout & Package

PI6C20400BLEX is packaged in a 28-pin TSSOP (L28, 173-mil wide), RoHS-compliant and halogen-free. Pin functions are validated per Diodes DS43443 Rev 1-2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and ICS843002AGILF, PI6C20400BLEX provides optimal balance of PCIe 3.0 compliance, SMBus configurability, and cost-effective discrete buffering-without over-specifying for Gen4 or embedding unnecessary oscillator circuitry.

Availability

PI6C20400BLEX is available at Aetrix Electronics and suitable for PCIe 3.0 root complex timing, server backplane clock distribution, and embedded NVMe controller clocking requiring stable component supply across extended production lifecycles.

Supply support for PI6C20400BLEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6C20400BLEX belongs to Diodes' Pericom timing portfolio, engineered specifically for PCIe 3.0 clock distribution with emphasis on jitter suppression, flexible control, and robust industrial operating conditions.

FAQ

What is the function of the IREF pin on PI6C20400BLEX?

The IREF pin connects to an external 475 Ω ±1% resistor to set the internal reference current (2.32 mA), which determines the differential output current (6 × IREF = 13.9 mA nominal). This enables precise control of output voltage swing (0.7 V into 100 Ω differential load) and ensures consistent drive strength across temperature and supply variations.

How does the PLL/BYPASS# pin affect clock path selection?

When PLL/BYPASS# is logic low, the device routes the SRC input through its internal PLL for 100 MHz output; when high, it bypasses the PLL for direct fanout across the 100–400 MHz input range. This selection is hardware-controlled and overrides SMBus register bit 1, enabling deterministic boot-time configuration without firmware dependency.

Can PI6C20400BLEX drive PCIe 4.0 links?

No. PI6C20400BLEX is specified for PCIe 3.0 (8 GT/s) with additive jitter tested up to 2–5 MHz high-frequency bands per PCIe 3.0 spec. Its maximum bypass frequency is 400 MHz, insufficient for PCIe 4.0's 16 GT/s (8 GHz fundamental), and it lacks PCIe 4.0-specific jitter filtering or equalization features.

What happens to outputs when both SRC_STOP# and PWRDWN# are asserted?

Both signals force all differential outputs (OUT0–OUT3 and complements) into high-impedance tristate. However, PWRDWN# has stricter requirements: when asserted, SDA and SCLK must also be tristated to prevent bus contention. SRC_STOP# alone allows SMBus communication to continue for dynamic reconfiguration.