Diodes Incorporated PI6C20400HE

Overview

PI6C20400HE from Pericom Semiconductor is a 3.3V differential clock buffer IC designed as a companion to the PI6C410B clock synthesizer for Intel PCI Express chipsets. It provides four differential clock output pairs (OUT0–OUT3), supports PLL or fanout operation, features <50ps output-to-output skew and <50ps cycle-cycle jitter, and enables tristate control via SMBus or dedicated OE pins for PCIe Gen1/Gen2 timing distribution.

For engineers reviewing the PI6C20400HE datasheet, PI6C20400HE pinout, PI6C20400HE application, or PI6C20400HE equivalent, key selection criteria include differential output current programmability (via IREF), SMBus-configurable PLL bandwidth and output enable states, low-jitter performance under 3.3V supply, and compatibility with Intel PCIe reference clock architectures requiring precise 1:4 fanout with stop/pwrdown sequencing.

Technical Context

The PI6C20400HE operates in either PLL mode (for jitter cleanup and frequency translation) or bypass/fanout mode (for zero-delay distribution), selected via the PLL/BYPASS# pin. Its current-mode differential outputs deliver 0.7V swing into 100Ω differential loads, with output current set by an external 475Ω IREF resistor yielding nominal 13.9mA per output pair.

Control logic integrates three independent assertion paths-SRC_STOP#, PWRDWN#, and SMBus register writes-to place outputs in high-impedance state. The device implements indexed block read/write over SMBus using 7-bit slave address 0x6E, supporting real-time configuration of output enables, PLL bandwidth, and SRC_STOP# response behavior without requiring hardware pin changes.

Key Specifications

Pinout & Package

PI6C20400HE is housed in a Pb-free, RoHS-compliant 28-pin SSOP package (209-mil width, JEDEC MO-153F/AE compliant), with separate power/ground domains for PLL core (VDD_A/VSS_A) and I/O (VDD/VSS).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar differential clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N502, the PI6C20400HE uniquely balances discrete PLL/fanout mode selection, SMBus-configurable output states, and PCIe-specific SRC_STOP#/PWRDWN# sequencing - making it optimal for flexible, standards-compliant PCIe timing architectures requiring both hardware and software control.

Availability

PI6C20400HE is available at Aetrix Electronics and suitable for PCIe root complex design, server backplane timing hubs, embedded NVMe controller synchronization, and industrial FPGA-based PCIe bridge interfaces requiring stable component supply and long-term lifecycle support.

Supply support for PI6C20400HE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-speed signal integrity solutions, acquired by Diodes Incorporated in 2016; its clock and interface portfolio continues under Diodes' timing division.

The PI6C20400HE belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically to meet Intel's reference clock distribution requirements for Gen1/Gen2 platforms with emphasis on low skew, configurable power-down, and SMBus configurability.

FAQ

What is the function of the IREF pin, and how does it affect output performance?

The IREF pin connects to an external 475Ω 1% resistor to set the nominal output current at 13.9mA per differential pair. This directly determines the 0.7V output swing into 100Ω differential loads. Deviations in IREF resistance cause proportional changes in output amplitude and drive strength, impacting signal integrity margin in PCIe AC-coupled channels.

Can the PI6C20400HE operate without an external crystal or reference clock?

No. The PI6C20400HE is a clock buffer, not a clock generator. It requires a differential input clock (SRC/SRC#) from an upstream source such as the PI6C410B synthesizer. It has no internal oscillator and cannot generate clock signals autonomously.

How does the SMBus interface interact with the OE_0 and OE_3 hardware pins?

SMBus register writes to Data Byte 1 bits 0,2,5,6 directly control individual output pair enables, overriding OE_0/OE_3 pin states. When SMBus output enable is active, the corresponding OE pin becomes irrelevant. This allows firmware to manage clock gating independently of hardware pin strapping.

What is the maximum allowable rise/fall time for the SRC_STOP# and PWRDWN# control signals?

The SRC_STOP# and PWRDWN# pins require monotonic transitions with rise/fall times ≤700ps (per AC specs). Exceeding this may cause metastability in internal state machines, leading to undefined output states or delayed tristate activation. A series resistor of 33Ω is recommended on each control line to dampen ringing and ensure clean edges.