Diodes Incorporated PI6C20400HEX

Overview

PI6C20400HEX from Pericom Semiconductor is a 3.3V differential clock buffer IC designed as a companion to PI6C410B for Intel PCI Express chipset timing distribution. It delivers four differential clock output pairs with <50ps skew and <50ps cycle-to-cycle jitter, supporting both PLL and fanout modes via programmable PLL bandwidth and PLL/BYPASS# control, used in PCIe Gen1/Gen2 root complex clock fanout.

For engineers reviewing the PI6C20400HEX datasheet, PI6C20400HEX pinout, PI6C20400HEX application, or PI6C20400HEX equivalent, key selection criteria include differential output current accuracy (±12% at 6×IREF), SMBus-controlled tristate enable per output pair, SRC_STOP#/PWRDWN# power management sequencing, and 28-pin SSOP (H28) package compatibility with PCIe reference clock routing constraints.

Technical Context

The PI6C20400HEX implements a dual-mode clock distribution architecture: either zero-delay PLL-based retiming or direct fanout bypass, selected by the PLL/BYPASS# input. Its current-mode differential outputs are calibrated via external IREF resistor (475Ω ±1%), delivering nominal 0.7V differential swing into 100Ω loads.

Control is implemented through three independent interfaces: asynchronous LVTTL pins (OE_0/OE_3, SRC_STOP#, PWRDWN#), SMBus-configurable registers (indexed block read/write at 7-bit address 0x6E), and dynamic PLL bandwidth selection (high/low) via PLL_BW#. Output tristate behavior is synchronized across all channels under PWRDWN# assertion with <300μs drive disable time.

Key Specifications

Pinout & Package

Package: 28-pin SSOP (H28), 209-mil wide, Pb-free and RoHS-compliant, JEDEC MO-153F/AE outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar differential clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N551, the PI6C20400HEX uniquely combines SMBus-per-pair enable, programmable PLL bandwidth, and current-mode 0.7V differential outputs-making it optimal for PCIe Gen2+ systems requiring flexible, low-noise, software-managed clock distribution without added synthesis complexity.

Availability

PI6C20400HEX is available at Aetrix Electronics and suitable for PCIe root complex clock distribution, server backplane timing fanout, and embedded NVMe controller timing requiring stable component supply and long-term industrial availability.

Supply support for PI6C20400HEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-speed interface and timing solutions, acquired by Diodes Incorporated in 2016; its timing portfolio remains widely deployed in PCIe, USB, and SATA infrastructure.

The PI6C20400 belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically for low-jitter, low-skew distribution of 100MHz differential reference clocks in multi-lane server and storage platforms.

FAQ

What is the function of the IREF pin and how is it configured?

The IREF pin connects to an external 475Ω ±1% resistor to ground, setting the reference current (2.32mA) that calibrates the current-mode differential outputs. This ensures precise 0.7V differential swing into 100Ω loads. The resistor must be placed close to the pin with minimal trace length to maintain accuracy; deviation beyond ±1% directly impacts output amplitude and jitter performance.

How does the PLL/BYPASS# pin affect timing behavior?

When PLL/BYPASS# is high, the device operates in PLL mode, providing zero-delay retiming and jitter cleanup of the SRC input. When low, it operates in fanout mode, passing the SRC clock directly with minimal propagation delay (2.5–6.5ns). Mode selection is static and must be set before clock operation begins; dynamic switching during operation is not supported.

Can PWRDWN# and SRC_STOP# be asserted simultaneously, and what is the resulting output state?

Yes, PWRDWN# and SRC_STOP# can be asserted simultaneously, and both force all differential outputs into high-impedance (tristate) mode. However, when PWRDWN# is active, the SDA and SCLK pins must also be tristated externally. The output disable sequence completes within 300μs, and recovery upon de-assertion takes <1ms, meeting PCIe Active State Power Management (ASPM) timing requirements.

What SMBus address and protocol does the PI6C20400HEX use for register access?

The PI6C20400HEX uses a fixed 7-bit SMBus slave address of 0x6E (1101110b) and supports only indexed block read and indexed block write protocols. Each transaction begins with the address byte and register offset, followed by a byte count and data bytes. No other SMBus commands (e.g., quick command, byte data) are supported; the device operates as a slave-only peripheral with no master capability.