Diodes Incorporated PI6C20400LE

Overview

PI6C20400LE from Pericom Semiconductor is a 3.3V differential clock buffer IC designed as a companion to PI6C410B for Intel PCI Express chipset timing distribution. It delivers four differential clock output pairs with <50ps skew and <50ps cycle-cycle jitter, operating in either PLL or fanout mode, and supports SMBus-controlled tristate enable/disable for all outputs in PCIe Gen1/Gen2 reference clock applications.

For engineers reviewing the PI6C20400LE datasheet, PI6C20400LE pinout, PI6C20400LE application, or PI6C20400LE equivalent, key selection criteria include differential output current programmability via IREF, PLL bandwidth selection (high/low), SRC_STOP#/PWRDWN# power management behavior, and SMBus register-accessible output enable control per channel.

Technical Context

The PI6C20400LE implements a current-mode differential output stage with programmable drive strength set by external 475Ω IREF resistor (nominal IOUT = 6 × IREF = 13.9mA), supporting 100Ω differential termination. Its dual-mode architecture allows direct fanout bypass of the internal PLL or closed-loop PLL operation with selectable bandwidth.

Control logic integrates three independent enable paths: dedicated OE_0/OE_3 pins for channel-specific output gating, global SRC_STOP# and PWRDWN# inputs with configurable polarity via OE_INV, and SMBus-addressable register bits (Data Byte 1) enabling/disabling each output pair individually under software control.

Key Specifications

Pinout & Package

Package: 28-pin TSSOP (JEDEC MO-153F/AE), 173-mil body width, Pb-free and RoHS-compliant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar differential clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N502, the PI6C20400LE uniquely balances PLL flexibility, per-output SMBus control, and PCIe-optimized skew/jitter-making it optimal for systems requiring field-upgradable clock management without redesigning the timing architecture.

Availability

PI6C20400LE is available at Aetrix Electronics and suitable for PCIe motherboard design, server backplane clock distribution, and embedded computing platforms requiring stable component supply and long-term lifecycle support.

Supply support for PI6C20400LE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed interface and timing solutions for datacenter, communications, and computing markets.

The PI6C20400 series targets PCIe Gen1/Gen2 clock distribution, emphasizing low skew, software-controllable outputs, and seamless interoperability with Pericom's PI6C410B clock synthesizer.

FAQ

What is the function of the IREF pin, and how does it affect output drive strength?

The IREF pin connects to a 475Ω 1% resistor to ground, setting the reference current (IREF = VDD/(3×RREF) ≈ 2.32mA). The differential outputs deliver 6×IREF = 13.9mA nominal into a 100Ω differential load, producing a 0.7V swing. Changing RREF directly scales all output currents proportionally, enabling adaptation to non-standard termination impedances.

How does the OE_INV pin modify the behavior of SRC_STOP# and PWRDWN#?

When OE_INV = 1 (high), the logic polarity of SRC_STOP#, PWRDWN#, and OE_0/OE_3 is inverted: active-low signals become active-high, and vice versa. This allows compatibility with system-level control logic that asserts enable signals high instead of low, eliminating external inverters in mixed-polarity control environments.

Can the PI6C20400LE operate without an external crystal or reference clock?

No. The PI6C20400LE is a clock buffer-not a clock generator-and requires a differential input clock (SRC/SRC#) from an external source such as the PI6C410B synthesizer. It has no internal oscillator or crystal interface; its PLL only cleans and redistributes the incoming reference signal.

What happens to the outputs during PWRDWN# assertion, and how quickly do they recover?

When PWRDWN# is asserted low, all outputs enter high-impedance state within <300μs, and the PLL core powers down. Upon de-assertion, outputs stabilize within <1ms. During this period, SCLK and SDA must be tristated to prevent bus contention, as the SMBus interface is disabled.