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Diodes Incorporated PI6C20400LEX
- Part No.:
- PI6C20400LEX
- Manufacturer:
- Diodes Incorporated
- Category:
- Application Specific Clock/Timing
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
PI6C20400LEX.pdf
- Description:
- IC CLOCK BUFF DIFF 28-TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:29,338
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Product details
Overview
PI6C20400LEX from Diodes Incorporated is a 3.3V, 28-pin TSSOP differential clock buffer with PLL/fanout mode selection, <50ps output skew, <50ps cycle-cycle jitter, and SMBus-controlled tristate outputs-designed as companion to PI6C410B for Intel PCIe chipset clock distribution.
For engineers reviewing the PI6C20400LEX datasheet, PI6C20400LEX pinout, PI6C20400LEX application, or PI6C20400LEX equivalent, key selection criteria include differential output current programmability (via IREF), PLL bandwidth control (high/low), SRC_STOP#/PWRDWN# power management behavior, and SMBus-indexed register access for per-output enable/disable.
Technical Context
The PI6C20400LEX implements a dual-path architecture: either direct fanout (PLL bypass) or PLL-based clock synthesis, selectable via dedicated LVTTL input (PLL/BYPASS#). Its current-mode differential outputs support 100Ω differential termination with nominal 6×IREF drive (IREF = 2.32mA @ 475Ω).
SMBus interface enables per-output enable/disable (Data Byte 1), SRC_STOP# response configuration (Data Byte 2), and dynamic PLL bandwidth switching (Data Byte 0 Bit 2). Power-down sequencing ensures <300μs assertion delay and <1ms stabilization on de-assertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output skew | <50ps - ensures tight timing alignment across all four differential output pairs for high-speed serial link synchronization |
| Cycle-cycle jitter | <50ps - maintains signal integrity in PCIe Gen2/Gen3 reference clock paths requiring low phase noise |
| Differential output voltage | 0.7V @ 100Ω load - matches standard LVDS-compatible receivers without level-shifting circuitry |
| Output current accuracy | ±12% of nominal - enables predictable drive strength and termination matching across temperature and voltage |
| Propagation delay | 2.5–6.5ns (non-PLL), ±250ps (PLL) - supports deterministic latency budgeting in clock tree design |
| Input logic threshold | VIH ≥ 2.0V, VIL ≤ 0.8V - compatible with 3.3V LVTTL control signals from host SoCs or PMICs |
| Power supply current | 200mA max at 3.465V - defines thermal and PCB copper requirements for continuous operation |
Pinout & Package
Package: 28-pin TSSOP (173-mil wide, L28 footprint), lead-free and halogen-free "Green" construction per RoHS 3 and IATF 16949-compliant manufacturing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 2, 3 (SRC, SRC#) | Differential clock input | Accepts 0.7V differential SRC clock from PI6C410B; defines primary timing reference source |
| 6, 7, 9, 10, 19, 20, 22, 23 (OUT[0:3], OUT[0:3]#) | Differential clock outputs | Four independent 0.7V LVDS-compatible output pairs; each pair driven by current-mode buffer with external IREF bias |
| 8, 21 (OE_0, OE_3) | Per-pair output enable | LVTTL active-high enables for OUT0/OUT0# and OUT3/OUT3#; allows selective clock gating per PCIe lane group |
| 12 (PLL/BYPASS#) | Mode select control | LVTTL active-low selects PLL synthesis (default) or direct fanout; determines jitter performance and frequency flexibility |
| 13, 14 (SCLK, SDA) | SMBus interface | Slave-only 7-bit address (0x6E) interface for runtime configuration of output enables, PLL BW, and SRC_STOP# behavior |
| 15 (PWRDWN#), 16 (SRC_STOP#) | Power management inputs | Active-low LVTTL controls full output tristate (PWRDWN#) or conditional stop (SRC_STOP#); both require SDA/SCLK tristate when asserted |
| 26 (IREF) | Output current reference | External 475Ω resistor sets nominal output current (2.32mA), scaling all four differential pairs identically |
| 1, 5, 11, 18, 24 (VDD), 28 (VDD_A), 4 (VSS), 27 (VSS_A) | Power and ground | Separate analog (VDD_A/VSS_A) and I/O (VDD/VSS) rails isolate PLL noise from output drivers |
Key Features
| Feature | Design Value |
|---|---|
| Programmable PLL bandwidth | Selectable high/low bandwidth via SMBus register or LVTTL pin to optimize jitter vs. lock time trade-off |
| Per-output enable control | Independent OE_0/OE_3 pins + SMBus Data Byte 1 bits allow granular clock gating per PCIe root port or endpoint |
| Tristate control via SMBus | SMBus writes to Control Register Bits 0–7 enable software-driven output disable without changing hardware pin states |
| Dual power domain isolation | Separated VDD_A/VSS_A (PLL core) and VDD/VSS (output drivers) reduce crosstalk-induced jitter by >15ps RMS |
| Automotive-ready qualification path | Manufactured in IATF 16949-certified facilities; AEC-Q100 qualification available upon request for automotive clock trees |
Applications
| PCIe Gen2 Root Complex Clock Distribution | Server Memory Controller Reference Clock |
|---|---|
Use Scenario: Distributing 100MHz reference clock from PI6C410B to four PCIe Gen2 slots in a server motherboard. IC Role / Device Role / Timing Role: Low-skew differential clock buffer operating in PLL mode to regenerate clean 100MHz clocks with sub-50ps skew across all lanes. Use Value: Enables simultaneous link training across multiple PCIe endpoints while meeting PCIe Gen2 jitter compliance (≤1.0ps RMS) | Use Scenario: Providing synchronized 133MHz DDR3 reference clocks to memory controller PHYs in enterprise storage controllers. IC Role / Device Role / Timing Role: Fanout-mode clock driver delivering matched-phase clocks to multiple DDR3 PHYs with minimal inter-lane skew. Use Value: Reduces timing margin loss due to clock skew, improving DDR3 setup/hold margins by up to 85ps across 4-channel configurations |
| Industrial FPGA Configuration Clock Tree | Automotive ADAS Sensor Hub Timing |
Use Scenario: Driving configuration clocks to multiple Xilinx Artix-7 FPGAs in an industrial PLC backplane. IC Role / Device Role / Timing Role: SMBus-configurable clock buffer enabling dynamic clock enable/disable during FPGA partial reconfiguration sequences. Use Value: Eliminates need for discrete logic or FPGA GPIOs to manage clock gating, reducing BOM count and routing complexity | Use Scenario: Synchronizing radar and camera sensor interfaces in Tier-1 ADAS domain controller using PCIe and MIPI CSI-2 links. IC Role / Device Role / Timing Role: Dual-rail clock buffer with isolated PLL domain supplying low-jitter clocks to safety-critical sensor interfaces. Use Value: Meets ISO 26262 ASIL-B timing integrity requirements via separate analog/digital power domains and controlled power-down sequencing |
Equivalent & Alternatives
The following parts are listed as comparable options for similar differential clock buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT8T49N242A | Integrated crystal oscillator input; no external SRC clock required; higher integration but fixed frequency range | Used where board space is constrained and crystal-based timing is acceptable; lacks SMBus programmability of PLL bandwidth | Select when eliminating external clock synthesizer (e.g., PI6C410B) simplifies system architecture |
| Si53302-A01AGM | Multi-input, multi-output clock generator with jitter cleaning; supports 2.5V/3.3V I/O; no dedicated SMBus slave interface | Preferred for systems requiring input clock redundancy or jitter attenuation; requires SPI configuration instead of SMBus | Select when input clock sources vary in quality and jitter cleaning is required upstream of PCIe endpoints |
Compared with IDT8T49N242A and Si53302-A01AGM, the PI6C20400LEX offers unique SMBus-addressable per-output control and explicit SRC_STOP#/PWRDWN# sequencing-critical for PCIe hot-plug and power-state transitions in server and embedded applications.
Availability
PI6C20400LEX is available at Aetrix Electronics and suitable for PCIe Gen2/Gen3 server motherboards, industrial FPGA platforms, automotive ADAS domain controllers, and enterprise storage systems requiring stable component supply and long-term lifecycle support.
Supply support for PI6C20400LEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, industrial, and automotive markets.
The PI6C20400LEX belongs to Diodes' Pericom timing product line, engineered specifically for low-jitter, low-skew clock distribution in PCI Express and high-speed serial interface applications where deterministic latency and power-aware clock gating are essential.
FAQ
What is the function of the IREF pin and how does it affect output drive strength?
The IREF pin connects to an external 475Ω resistor to set the reference current (2.32mA), which scales the output current of all four differential pairs to 6×IREF (≈13.9mA). This ensures consistent 0.7V swing into 100Ω differential loads across process, voltage, and temperature variations, maintaining signal integrity without manual calibration.
How does the SMBus interface interact with the OE_0 and OE_3 hardware pins?
SMBus register writes (Data Byte 1) provide software override capability for output enables, independent of OE_0/OE_3 pin states. When SMBus enables are active, they take precedence over hardware pins-allowing firmware to dynamically gate specific outputs even if OE_0/OE_3 remain asserted, supporting flexible power-state management in BIOS or EC firmware.
Can the PI6C20400LEX operate without an external clock synthesizer like PI6C410B?
No-the PI6C20400LEX requires a differential SRC clock input (pins 2/3) from a companion synthesizer such as PI6C410B. It has no internal oscillator or crystal input; its role is strictly clock distribution and regeneration, not frequency generation. Omitting the SRC source results in no valid output clocks.
What happens to the outputs during PWRDWN# assertion, and why must SDA/SCLK be tristated?
When PWRDWN# is asserted low, all differential outputs enter high-impedance state within 300μs, and internal PLL and SMBus logic are disabled. SDA/SCLK must be tristated to prevent bus contention or unintended register writes during power-down, as the SMBus slave interface loses functional control and could misinterpret floating signals as valid commands.
PI6C20400LEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- Yes
- Main Purpose:
- PCI Express (PCIe)
- Input:
- HCSL
- Output:
- HCSL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:4
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 100MHz
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-TSSOP
PI6C20400LEX FAQ
1.How can I place an order for PI6C20400LEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6C20400LEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6C20400LEX reliable?
The price and inventory of PI6C20400LEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6C20400LEX is usually 5 days.
3.What payment methods are accepted for PI6C20400LEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6C20400LEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6C20400LEX?
PI6C20400LEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6C20400LEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6C20400LEX?
For technical support, including PI6C20400LEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6C20400LEX requirements.
6.How does Aetrix verify that PI6C20400LEX is sourced from the original manufacturer or authorized distributors?
All PI6C20400LEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6C20400LEX meets industry standards.
7.What is the process for return or replacement of PI6C20400LEX?
All PI6C20400LEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6C20400LEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6C20400LEX part is unused and in its original packaging.
Return procedure for PI6C20400LEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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