Diodes Incorporated PI6C20800BAE

Overview

PI6C20800BAE from Pericom Semiconductor is a PCIe 3.0-compliant, 1:8 differential HCSL clock buffer with PLL/fanout mode selection, <50 ps output-to-output skew, 60 ps cycle-to-cycle jitter, and SMBus programmability - designed to distribute SRC clocks from Intel server chipset clock generators to eight HCSL loads in high-density server backplanes.

For engineers reviewing the PI6C20800BAE datasheet, PI6C20800BAE pinout, PI6C20800BAE application, or PI6C20800BAE equivalent, key selection criteria include PCIe 3.0 additive phase jitter (<1.5 ps RMS), programmable PLL bandwidth (high/low), tristate control via SRC_STOP# and PWRDWN#, and industrial-grade variant support (PI6C20800BI).

Technical Context

The PI6C20800BAE operates in either PLL mode (95–105 MHz input, low-jitter regeneration) or bypass mode (95–400 MHz, minimal latency), with configurable PLL bandwidth (high/low) via PLL_BW# pin or SMBus register. It supports SRC clock division-by-2 when SRC_DIV# is asserted.

Output enable is per-channel (OE[0:7]) or global (SRC_STOP#, PWRDWN#), with OE_INV enabling polarity inversion. The device implements current-mode HCSL outputs (IOUT ≈ 13.9 mA nominal, set by 475 Ω IREF resistor), and provides LOCK status indication for PLL lock detection.

Key Specifications

Pinout & Package

Package: 48-pin TSSOP (240-mil wide, Pb-free & Green, package code A). Pin pitch: 0.5 mm; body width: 6.1 mm; height: 1.2 mm max.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 3.0 clock buffer applications.

Compared with IDT 8T49N242 and ON Semi NB3N551, the PI6C20800BAE uniquely combines native HCSL drive, pin-strapped SRC_DIV#, hardware-fast tristate, and SMBus configurability - making it optimal for Intel server reference designs requiring PCIe 3.0 compliance and field-upgradable timing control.

Availability

PI6C20800BAE is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch card development, and Intel C620 chipset integration requiring stable component supply across extended production lifecycles.

Supply support for PI6C20800BAE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal-integrity solutions for datacenter and communications infrastructure.

The PI6C20800B belongs to Pericom's PCIe 3.0 clock buffer product line, engineered specifically to meet Intel server platform timing specifications including skew, jitter, and power-management responsiveness.

FAQ

What is the function of the IREF pin on PI6C20800BAE?

The IREF pin connects to an external 475 Ω ±1% resistor to set the reference current (IREF = VDD / 3RREF ≈ 2.32 mA), which determines the nominal HCSL output current (6 × IREF = 13.9 mA). This current-mode architecture ensures consistent drive strength across voltage and temperature variations without requiring feedback calibration.

Does PI6C20800BAE support both PLL and bypass modes simultaneously?

No - PLL/BYPASS# is a single control pin that selects one operational mode: logic LOW configures fanout (bypass) mode for minimal latency; logic HIGH enables PLL mode for jitter cleanup. Mode selection is static during operation and cannot be toggled dynamically without resetting the device or reconfiguring via SMBus.

How does the LOCK pin behave during power-up and PLL acquisition?

The LOCK pin is an open-drain 3.3 V output that remains LOW until the PLL achieves frequency and phase lock, then transitions HIGH and latches. Lock time is typically <1 ms after PWRDWN# deassertion. The latch holds LOCK HIGH even if the input clock is temporarily lost, requiring PWRDWN# toggle or power cycle to reset.

Can OE[0:7] pins be used to disable individual outputs while others remain active?

Yes - each OE[n] pin controls its corresponding OUTn/OUTn# pair independently. When OE[n] = HIGH, the pair drives; when LOW, it enters high-impedance state. This enables per-lane power gating in multi-root PCIe configurations without affecting other active lanes or requiring SMBus transactions.