Diodes Incorporated PI6C20800BAEX
- Part No.:
- PI6C20800BAEX
- Manufacturer:
- Diodes Incorporated
- Category:
- Application Specific Clock/Timing
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
PI6C20800BAEX.pdf
- Description:
- IC CLOCK BUFFER 1:8 48TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:937
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Product details
Overview
PI6C20800BAEX from Diodes Incorporated is a PCIe 3.0-compliant, 1:8 differential clock buffer with integrated PLL, designed as a companion to Intel server chipset clock generators. It distributes a 95–400 MHz differential SRC clock across eight HCSL output pairs, supports input divide-by-2, offers <50 ps output skew (PI6C20800B), and operates at 3.3 V for server motherboard timing distribution.
For engineers reviewing the PI6C20800BAEX datasheet, PI6C20800BAEX pinout, PI6C20800BAEX application, or PI6C20800BAEX equivalent, this device is selected for low-jitter PCIe 3.0 clock fanout in high-density server platforms requiring SMBus programmability, tristate control, and industrial-grade thermal stability.
Technical Context
The PI6C20800BAEX implements a dual-mode architecture: PLL mode (95–105 MHz input) for jitter cleanup and bypass mode (95–400 MHz) for zero-delay fanout. Its phase jitter filter meets PCIe 3.0 additive RMS phase jitter requirements (<1.5 ps over 2–5 MHz integration bandwidth).
It features SMBus-controlled register access for dynamic configuration of PLL bandwidth, output enable per channel, SRC_STOP# behavior, and power-down state. The device uses current-mode differential outputs with external IREF resistor (475 Ω) to set nominal 13.9 mA per HCSL pair (6 × IREF), ensuring consistent 100 Ω differential termination compliance.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Frequency Range | 95–105 MHz (PLL mode); 95–400 MHz (bypass mode) - enables compatibility with PCIe 3.0 reference clocks and legacy PCIe 1.0/2.0 sources. |
| Output Skew | <50 ps (PI6C20800B) - ensures tight timing alignment across all 8 HCSL output pairs for multi-lane PCIe slot synchronization. |
| Cycle-to-Cycle Jitter | <60 ps (differential waveform) - maintains signal integrity under high-speed switching for reliable receiver sampling margin. |
| Phase Jitter (PCIe 3.0) | 1.115–1.425 ps RMS (1st harmonic, 2–5 MHz BW) - satisfies PCIe 3.0 specification for additive jitter at receiver input. |
| Supply Voltage | 3.3 V ±5% (VDD and VDD_A) - matches standard server rail infrastructure and simplifies power delivery design. |
| Operating Temperature | 0°C to +70°C (commercial grade) - validated for sustained operation in air-cooled server chassis environments. |
| IREF Resistor | 475 Ω ±1% - sets nominal 2.32 mA reference current, enabling precise 13.9 mA HCSL output drive into 100 Ω differential loads. |
Pinout & Package
PI6C20800BAEX is housed in a 48-pin TSSOP (240 mil wide, package code A), with separate analog (VDD_A/VSS_A) and I/O (VDD/VSS) power domains to isolate PLL noise from output drivers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, SRC_DIV# | Control input | Active-low LVTTL signal selecting input frequency division by 2 - enables 100 MHz input → 50 MHz output derivation for auxiliary clock domains. |
| 4–5, SRC/SRC# | Differential input | 0.7 V differential HCSL input pair accepting clock from upstream PCIe generator - requires AC-coupled 100 Ω termination. |
| 6–7,14–15,35–36,43–44, OE[0:7] | Per-output enable | Eight independent 3.3 V LVTTL inputs enabling/disabling each output pair - allows dynamic lane shutdown without affecting other outputs. |
| 8–9,12–13,16–17,20–21,29–30,33–34,37–38,41–42, OUT[0:7]/OUT[0:7]# | Differential output | Eight HCSL output pairs (0.7 V swing, 100 Ω diff) - each pair drives one PCIe lane's REFCLK+/- with matched routing capability. |
| 22, PLL/BYPASS# | Mode select | Active-low LVTTL input selecting PLL (jitter filtering) or bypass (zero-delay fanout) operation - determines jitter performance vs. latency trade-off. |
| 23–24, SCLK/SDA | SMBus interface | Two-wire serial bus interface supporting indexed block read/write - enables runtime reconfiguration of PLL bandwidth and output states. |
| 45, LOCK | Status output | Latched 3.3 V LVTTL high when PLL achieves lock - provides hardware-ready signal for system BIOS or BMC initialization sequencing. |
| 46, IREF | Current reference | Analog input connecting external 475 Ω resistor - sets output current scaling factor (6× IREF) for accurate HCSL voltage levels. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable PLL bandwidth | Selectable high/low PLL loop bandwidth via SMBus or pin control - optimizes jitter attenuation vs. tracking response for varying source stability. |
| Per-output tristate control | Independent OE[0:7] pins allow selective disabling of any output pair while others remain active - supports hot-plug PCIe slot management. |
| Low skew distribution | <50 ps max output-to-output skew across all 8 channels - guarantees simultaneous edge arrival for multi-lane PCIe Gen3 receivers. |
| Power management integration | Hardware SRC_STOP# and PWRDWN# inputs plus SMBus control enable coordinated low-power states - reduces idle power in server standby modes. |
| HCSL output compliance | Current-mode driver with 475 Ω IREF sets 13.9 mA nominal output current - delivers 0.7 V differential swing into 100 Ω loads meeting PCIe HCSL spec. |
Applications
| Server Motherboard Clock Distribution | PCIe Switch Timing Interface |
|---|---|
|
Use Scenario: Distributing a single PCIe 3.0 reference clock from a central clock generator to eight discrete PCIe slots on a 2U rack server motherboard. IC Role / Device Role / Timing Role: Low-skew, jitter-filtered 1:8 HCSL clock buffer operating in PLL mode to clean upstream clock noise before fanout. Use Value: Ensures all eight PCIe Gen3 lanes meet 1.5 ps RMS additive jitter limit at receiver input, preventing link training failures under thermal stress. |
Use Scenario: Providing synchronized REFCLK signals to a PCIe 3.0 switch IC (e.g., Broadcom BCM57504) with multiple downstream ports. IC Role / Device Role / Timing Role: Bypass-mode clock fanout buffer delivering zero-delay, low-skew copies of the upstream generator clock to switch REFCLK inputs. Use Value: Eliminates inter-port clock skew that could cause timing violations during cross-port DMA transfers, improving switch throughput consistency. |
| Intel C620 Chipset Companion Buffer | Enterprise SSD Controller Reference Clock |
|
Use Scenario: Supporting Intel C620-series server chipsets requiring dedicated REFCLK for SATA, USB 3.0, and PCIe root complexes. IC Role / Device Role / Timing Role: Multi-function clock distributor using SMBus to dynamically enable/disable outputs per subsystem requirement. Use Value: Reduces BOM count by consolidating three separate clock buffers into one device with configurable output assignment. |
Use Scenario: Delivering low-jitter 100 MHz REFCLK to NVMe SSD controller ASICs in enterprise storage arrays. IC Role / Device Role / Timing Role: High-reliability clock buffer operating in industrial temperature range (via PI6C20800BI variant) with LOCK status monitoring. Use Value: Maintains PCIe 3.0 link stability during sustained write workloads where controller thermal throttling would otherwise degrade clock integrity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe 3.0 clock buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IDT 8P34S1208NLGI | 8-output LVDS/LVPECL buffer; no integrated PLL; higher supply current (320 mA typical) | Requires external jitter cleaner for PCIe 3.0 compliance; suited for mixed-signal systems needing LVDS outputs | Select when LVDS signaling or higher drive strength is required, and external jitter filtering is acceptable. |
| ON Semi NB3N551DR2G | 4-output HCSL buffer; no SMBus interface; fixed PLL bandwidth; 32-pin QFN package | Limited channel count and configurability; lacks per-output enable and dynamic PLL tuning | Choose for cost-sensitive, space-constrained designs with ≤4 PCIe lanes and static configuration needs. |
Compared with IDT 8P34S1208NLGI and ON Semi NB3N551DR2G, the PI6C20800BAEX uniquely combines 8-channel HCSL output, integrated PCIe-optimized PLL, SMBus programmability, and per-output tristate control - making it the only solution meeting full Intel server platform clock distribution requirements in a single 48-TSSOP package.
Availability
PI6C20800BAEX is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch timing interfaces, Intel C620 chipset support, and enterprise SSD controller reference clocking requiring stable component supply across extended production cycles.
Supply support for PI6C20800BAEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, industrial, and communications markets.
The PI6C20800BAEX belongs to Diodes' Pericom timing product line, engineered specifically for PCIe 3.0 and server-grade clock distribution - emphasizing low jitter, high channel density, and robust power management for datacenter infrastructure.
FAQ
What is the function of the IREF pin on PI6C20800BAEX?
The IREF pin connects to an external 475 Ω ±1% resistor to set the internal reference current (2.32 mA), which scales the HCSL output drive strength to 13.9 mA per differential pair. This ensures precise 0.7 V differential swing into 100 Ω loads and maintains PCIe 3.0 electrical compliance across voltage and temperature variations.
How does the PLL/BYPASS# pin affect timing performance?
When PLL/BYPASS# is asserted low, the device operates in PLL mode with jitter filtering optimized for 95–105 MHz inputs, reducing additive phase jitter to ≤1.43 ps RMS. When deasserted high, it enters bypass mode for zero-delay fanout across 95–400 MHz, trading jitter cleanup for minimal propagation delay variation (±7.5 ns).
Can PI6C20800BAEX support both commercial and industrial temperature ranges?
The PI6C20800BAEX is rated for 0°C to +70°C (commercial). For industrial operation (–40°C to +85°C), the pin-compatible PI6C20800BIAEX variant must be used - it shares identical functionality and pinout but is characterized and screened for extended thermal reliability in harsher environments.
What happens to outputs when SRC_STOP# and PWRDWN# are both asserted?
When either SRC_STOP# or PWRDWN# is low, all outputs go to high-impedance (tristate). If both are asserted, outputs remain tristated, but PWRDWN# additionally forces SCLK/SDA to high-impedance and reduces supply current to ≤12 mA - entering deepest power-down state with fastest wake-up time (<1 ms).
PI6C20800BAEX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- -
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- Yes
- Main Purpose:
- PCI Express (PCIe)
- Input:
- HCSL
- Output:
- HCSL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:8
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 400MHz
- Voltage - Supply:
- 3.135V ~ 3.465V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-TSSOP
PI6C20800BAEX FAQ
1.How can I place an order for PI6C20800BAEX through Aetrix?
Please submit a Request for Quotation (RFQ) for PI6C20800BAEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PI6C20800BAEX reliable?
The price and inventory of PI6C20800BAEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6C20800BAEX is usually 5 days.
3.What payment methods are accepted for PI6C20800BAEX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6C20800BAEX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PI6C20800BAEX?
PI6C20800BAEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PI6C20800BAEX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PI6C20800BAEX?
For technical support, including PI6C20800BAEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6C20800BAEX requirements.
6.How does Aetrix verify that PI6C20800BAEX is sourced from the original manufacturer or authorized distributors?
All PI6C20800BAEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6C20800BAEX meets industry standards.
7.What is the process for return or replacement of PI6C20800BAEX?
All PI6C20800BAEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6C20800BAEX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PI6C20800BAEX part is unused and in its original packaging.
Return procedure for PI6C20800BAEX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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