Diodes Incorporated PI6C20800BIAE

Overview

PI6C20800BIAE from Pericom Semiconductor is a PCIe 3.0-compliant, 1:8 differential HCSL clock buffer with integrated PLL, designed to distribute SRC clock signals from Intel server chipset clock generators. It delivers eight matched differential output pairs, supports PLL or bypass operation, features <50 ps output-to-output skew, <60 ps cycle-to-cycle jitter, and operates at 3.3 V across –40°C to +85°C industrial temperature range.

For engineers reviewing the PI6C20800BIAE datasheet, PI6C20800BIAE pinout, PI6C20800BIAE application, or PI6C20800BIAE equivalent, key selection criteria include PCIe 3.0 phase jitter compliance (≤1.425 ps RMS additive jitter), programmable PLL bandwidth, SMBus-controlled tristate enable per output, and industrial-grade thermal stability for server motherboard timing distribution.

Technical Context

The PI6C20800BIAE implements a dual-mode clock distribution architecture: PLL mode (95–105 MHz input) for jitter cleanup and bypass mode (95–400 MHz) for low-latency fanout. Its current-mode HCSL outputs are calibrated via external 475 Ω IREF resistor to deliver 13.8 mA nominal differential drive into 100 Ω loads.

Control logic integrates three independent tristate mechanisms-SRC_STOP#, PWRDWN#, and SMBus register bits-with OE[0:7] enabling individual output pairs. The LOCK signal latches PLL lock status, and PLL_BW# selects high- or low-bandwidth loop response to optimize jitter suppression for PCIe 3.0 spectral requirements.

Key Specifications

Pinout & Package

Package: 48-pin TSSOP (240-mil wide, Pb-free & Green, package code A), JEDEC MO-153F/ED compliant, with separate analog (VDD_A/VSS_A) and digital (VDD/VSS) power/ground domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 3.0 clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N551, the PI6C20800BIAE uniquely balances PCIe 3.0 jitter compliance, industrial temperature support, and granular SMBus configurability - making it optimal for server motherboard clock trees requiring field-upgradable timing behavior without redesign.

Availability

PI6C20800BIAE is available at Aetrix Electronics and suitable for server motherboard design, PCIe 3.0 switch timing, and enterprise SSD controller applications requiring stable component supply across extended product lifecycles.

Supply support for PI6C20800BIAE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal-integrity solutions for datacenter and communications infrastructure.

The PI6C20800BIAE belongs to Pericom's PCIe 3.0 clock buffer product line, engineered specifically for low-jitter, high-reliability clock distribution in Intel server platforms with strict thermal and EMI constraints.

FAQ

What is the function of the IREF pin on PI6C20800BIAE?

The IREF pin connects to an external 475 Ω 1% resistor to set the reference current (IREF = 2.32 mA), which directly scales the differential output current to 13.8 mA (6 × IREF). This calibration ensures consistent HCSL drive strength across process, voltage, and temperature variations, meeting PCIe 3.0 amplitude and slew rate requirements.

How does the PLL/BYPASS# pin affect clock distribution behavior?

When PLL/BYPASS# is LOW, the device operates in PLL mode for jitter attenuation; when HIGH, it bypasses the PLL for minimal propagation delay. In PLL mode, input frequencies are constrained to 95–105 MHz, while bypass mode supports 95–400 MHz. The LOCK signal is only valid in PLL mode and indicates stable phase lock after ≥1 ms.

Can PI6C20800BIAE drive non-HCSL loads such as LVDS or LVPECL?

No. The PI6C20800BIAE is optimized exclusively for HCSL loads (100 Ω differential, 0.7 V swing). Its current-mode output stage lacks the voltage compliance or termination flexibility required for LVDS (±350 mV) or LVPECL (+2.0 V common-mode). Using it with non-HCSL receivers risks signal integrity failure and violates PCIe 3.0 electrical specifications.

What happens to output states during PWRDWN# assertion?

When PWRDWN# is asserted LOW, all outputs enter high-impedance state, the PLL is disabled, and power consumption drops to ≤12 mA. Critically, SCLK and SDA must be tristated before PWRDWN# activation to prevent bus contention; the LOCK signal remains latched but no longer updates. Recovery time to full operation is <1 ms after PWRDWN# deassertion.