Diodes Incorporated PI6C20800BIAEX

Overview

PI6C20800BIAEX from Diodes Incorporated is a PCIe 3.0-compliant, 1:8 differential HCSL clock buffer with integrated PLL, designed as a companion to Intel server chipset clock generators. It distributes a differential SRC clock across eight output pairs with <50ps output-to-output skew, programmable PLL bandwidth, and SMBus-controlled tristate enable-used in high-reliability server motherboard timing subsystems.

For engineers reviewing the PI6C20800BIAEX datasheet, PI6C20800BIAEX pinout, PI6C20800BIAEX application, or PI6C20800BIAEX equivalent, key selection criteria include PCIe 3.0 additive jitter compliance (≤1.425 ps RMS), 3.3V operation, industrial temperature range (–40°C to +85°C), and SMBus-configurable PLL/fanout mode.

Technical Context

The PI6C20800BIAEX implements a dual-mode architecture: PLL-enabled mode for jitter cleanup and fanout mode for low-latency distribution. Its phase-locked loop supports selectable bandwidth (high/low) via dedicated LVTTL control pins and delivers ≤1.425 ps RMS additive phase jitter at PCIe 3.0 1st harmonic (2 MHz & 4 MHz).

It accepts a 95–400 MHz differential SRC input (HCSL-compatible), provides eight matched differential HCSL outputs (0.7V common-mode), and supports dynamic power management via SRC_STOP# and PWRDWN# inputs that force tristate on all outputs within <300 µs.

Key Specifications

Pinout & Package

PI6C20800BIAEX is housed in a 48-pin TSSOP (240-mil wide, package code A), RoHS-compliant and halogen-free ("Green"). The package features split power/ground rails (VDD/VSS for outputs, VDD_A/VSS_A for PLL) to isolate analog PLL circuitry from digital I/O switching noise.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and ICS843002AGI, PI6C20800BIAEX uniquely balances PCIe 3.0 jitter compliance, per-output enable control, and compatibility with existing PI6C410 clock synthesizers - making it optimal for Intel server platform upgrades requiring minimal schematic change.

Availability

PI6C20800BIAEX is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch timing subsystems, and enterprise SSD controller applications requiring stable component supply across extended product lifecycles.

Supply support for PI6C20800BIAEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for computing and communications infrastructure.

The PI6C20800BIAEX belongs to Diodes' Pericom timing product line, engineered specifically for PCIe 3.0 server and storage applications where low additive jitter, industrial temperature operation, and flexible configuration are mandatory.

FAQ

What is the function of the IREF pin, and how does it affect output voltage?

The IREF pin connects to an external 475Ω 1% resistor to set the nominal output current (2.32mA). This current determines the HCSL output voltage swing: with 100Ω differential load, it yields 600–900mV peak-to-peak. Deviation beyond ±12% of nominal current alters VOH/VOL, potentially violating PCIe 3.0 eye mask specifications.

How does the PLL/BYPASS# pin affect propagation delay and jitter performance?

When PLL/BYPASS# is HIGH, the device operates in PLL mode with jitter filtering but adds ±250ps propagation delay variation (PI6C20800B). When LOW, it enters bypass mode with ±7.5ns delay variation but no jitter cleanup - selecting mode requires matching system-level jitter budget and timing closure constraints.

Can OE[0:7] pins be used to disable individual outputs while others remain active?

Yes. Each OE[n] pin independently controls one output pair: HIGH enables OUT[n]/OUT[n]#, LOW disables it. This allows dynamic lane shutdown in multi-slot servers without affecting other PCIe links - verified with simultaneous toggling of OE[0] and OE[7] under full thermal load.

What is the significance of the LOCK pin, and how is it used in system initialization?

The LOCK pin is a latched 3.3V LVTTL output that transitions HIGH only after PLL achieves stable lock (typically within 3ms of power-up). It serves as hardware-ready signal for BIOS/firmware to initiate PCIe enumeration - not asserted during PWRDWN# or SRC_STOP# assertion, ensuring safe reset sequencing.