Diodes Incorporated PI6C20800SAE

Overview

PI6C20800SAE from Pericom Semiconductor is a PCIe®-compliant 1:8 HCSL differential clock buffer with PLL/fanout mode selection, eight differential output pairs (OUT0–OUT7), <50ps output skew (PI6C20800S variant), and SMBus-controlled tristate enable. It operates at 3.3V, supports SRC clock division-by-2, and targets Intel server chipset clock distribution systems.

For engineers reviewing the PI6C20800SAE datasheet, PI6C20800SAE pinout, PI6C20800SAE application, or PI6C20800SAE equivalent, key selection criteria include differential HCSL output compliance, programmable PLL bandwidth, SMBus-configurable output enable per channel, industrial temperature support (via SI variant), and 48-pin TSSOP packaging with Pb-free/Green compliance.

Technical Context

The PI6C20800SAE implements a dual-mode architecture: PLL mode (95–105 MHz input) for jitter filtering and fanout mode (95–400 MHz) for low-latency distribution. Its current-mode HCSL outputs deliver 0.7V differential swing into 100Ω loads with ±12% current accuracy via external 475Ω IREF resistor.

Control is split across dedicated LVTTL pins (SRC_STOP#, PWRDWN#, OE[0:7], PLL/BYPASS#) and an SMBus interface supporting indexed block read/write to four control registers. The LOCK signal latches PLL lock status, and OE_INV enables global inversion of enable/power control logic.

Key Specifications

Pinout & Package

PI6C20800SAE is packaged in a 48-pin TSSOP (Package Code A), 240-mil wide, Pb-free and RoHS-compliant. Pin pitch is 0.5 mm; body dimensions are 12.6 × 6.2 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N551, PI6C20800SAE uniquely balances per-output SMBus/LVTTL control, PLL/fanout mode switching, and PCIe-specific jitter performance in a discrete buffer form factor-making it optimal for modular server clock architectures requiring field-upgradeable timing control.

Availability

PI6C20800SAE is available at Aetrix Electronics and suitable for Intel server platform clock distribution, PCIe Gen1/Gen2 slot timing, and industrial backplane systems requiring stable component supply, long-term lifecycle support, and Pb-free compliance.

Supply support for PI6C20800SAE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal integrity solutions for computing and communications infrastructure.

The PI6C20800SAE belongs to Pericom's PCIe clock buffer product line, designed specifically to complement Intel server clock generators and meet PCIe Gen1/Gen2 electrical and jitter specifications in multi-slot, multi-processor platforms.

FAQ

What is the function of the IREF pin on PI6C20800SAE?

The IREF pin connects to an external 475Ω 1% resistor to set the reference current (IREF = 2.32 mA), which determines the nominal output current (IOUT = 6 × IREF ≈ 13.9 mA). This establishes the 0.7V HCSL differential output swing into a 100Ω load and must be populated for correct output drive strength and voltage compliance.

How does the PLL/BYPASS# pin affect clock distribution behavior?

When PLL/BYPASS# is LOW, the device operates in PLL mode for jitter filtering (input 95–105 MHz); when HIGH, it operates in bypass/fanout mode for low-latency distribution (input 95–400 MHz). This pin directly controls whether the internal PLL is engaged, altering propagation delay, jitter performance, and frequency range support.

Can PI6C20800SAE drive PCIe Gen3 lanes?

No. PI6C20800SAE is specified for PCIe Gen1/Gen2 (100 MHz/2.5 GT/s and 5 GT/s), with AC characteristics validated up to 400 MHz in bypass mode and 105 MHz in PLL mode. Its jitter performance, output rise/fall times, and HCSL level compliance do not meet PCIe Gen3 (8 GT/s) requirements, which demand tighter additive jitter and different signaling standards.

What happens to outputs when both SRC_STOP# and PWRDWN# are asserted?

Both SRC_STOP# and PWRDWN# force outputs into high-impedance (tristate) mode. PWRDWN# takes precedence: when asserted, SCLK and SDA must also be tristated, and total supply current drops to 12 µA. SRC_STOP# alone tristates outputs while maintaining active PLL and SMBus functionality, allowing dynamic stop/resume without full power cycle.