Diodes Incorporated PI6C20800SAEX

Overview

PI6C20800SAEX from Diodes Incorporated is a PCIe®-compliant 1:8 HCSL differential clock buffer with PLL/fanout mode selection, 95–400 MHz input frequency support, <50 ps output-to-output skew (PI6C20800S grade), and SMBus programmable control. It serves as a companion to PI6C410BS clock generators in Intel server chipset applications, distributing SRC differential clocks to eight HCSL output pairs while supporting power-down, tristate, and divide-by-2 functions.

For engineers reviewing the PI6C20800SAEX datasheet, PI6C20800SAEX pinout, PI6C20800SAEX application, or PI6C20800SAEX equivalent, this device is selected for high-integrity PCIe Gen1/Gen2 timing distribution where low additive jitter (<1 ps RMS), precise skew control, SMBus-configurable PLL bandwidth, and industrial-grade variants are required.

Technical Context

The PI6C20800SAEX implements a dual-mode architecture: PLL mode enables jitter filtering for PCIe reference clocks (95–105 MHz), while bypass mode supports wideband fanout (95–400 MHz). Its current-mode HCSL outputs deliver 0.7 V differential swing into 100 Ω loads with ±12% current accuracy via external IREF resistor (475 Ω).

Control is implemented through dedicated LVTTL pins (SRC_STOP#, PWRDWN#, OE[0:7], PLL/BYPASS#) and an SMBus slave interface supporting indexed block read/write. The LOCK signal asserts high upon PLL lock, and OE_INV allows inversion of enable/control logic polarity.

Key Specifications

Pinout & Package

PI6C20800SAEX is housed in a 48-pin TSSOP (A) package, 240-mil wide, with exposed thermal pad not connected internally. Pin assignments follow JEDEC MO-153AA outline and support 3.3 V LVTTL/SMBus signaling levels.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock distribution applications.

Compared with IDT8T49N242A and NB3N551, PI6C20800SAEX uniquely balances programmable jitter filtering, per-output control, and commercial-grade reliability in a compact TSSOP package-making it optimal for scalable PCIe Gen2 server clock trees requiring firmware-managed lane power states.

Availability

PI6C20800SAEX is available at Aetrix Electronics and suitable for PCIe server motherboards, Intel chipset reference designs, enterprise storage controllers, and high-density accelerator cards requiring stable component supply and long-term lifecycle support.

Supply support for PI6C20800SAEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6C20800SAEX belongs to Diodes' Pericom timing portfolio, engineered specifically for PCIe Gen1/Gen2 clock distribution in server and storage platforms where low skew, programmable jitter filtering, and SMBus configurability are critical design requirements.

FAQ

What is the function of the IREF pin, and how is it configured?

The IREF pin sets the nominal output current for all eight HCSL output pairs using an external 475 Ω 1% resistor connected to VDD. This establishes a 2.32 mA reference current, which scales to 13.9 mA (6×) at each output pair, ensuring compliant 0.7 V differential swing into 100 Ω loads. Resistor tolerance directly impacts output amplitude accuracy (±12% typical).

How does the PLL/BYPASS# pin affect timing performance?

When PLL/BYPASS# is HIGH, the device operates in PLL mode for jitter filtering (95–105 MHz), reducing additive phase jitter to <1 ps RMS for PCIe Gen2 compliance. When LOW, it enters bypass mode (95–400 MHz), eliminating PLL-induced latency and phase noise but passing input jitter unfiltered - ideal for Gen1 or low-delay fanout applications.

Can PI6C20800SAEX support both commercial and industrial temperature ranges?

No - PI6C20800SAEX is the commercial-grade variant rated for 0 °C to +70 °C ambient. The industrial version is PI6C20800SIAEX, specified for –40 °C to +85 °C and marked with 'I' in the part number. Both share identical pinout, functionality, and package (48-pin TSSOP), differing only in temperature qualification and screening.

What happens to outputs when both SRC_STOP# and PWRDWN# are asserted LOW?

Both signals force all outputs to tristate, but PWRDWN# takes precedence: it disables internal circuitry, reduces supply current to ≤12 µA (tristate) or ≤80 µA (driven), and requires SCLK/SDA to be tristated. SRC_STOP# alone stops clock distribution while retaining output drive capability; asserting both ensures lowest power state with guaranteed high-impedance outputs.