Diodes Incorporated PI6C20800SIAE

Overview

PI6C20800SIAE from Pericom Semiconductor is an industrial-grade, 48-pin TSSOP, PCIe®-compliant 1:8 HCSL differential clock buffer with PLL/fanout mode selection, <60ps output-to-output skew, <70ps cycle-to-cycle jitter, and SMBus programmable control-designed as a companion to PI6C410BS clock generators in Intel server chipset timing trees.

For engineers reviewing the PI6C20800SIAE datasheet, PI6C20800SIAE pinout, PI6C20800SIAE application, or PI6C20800SIAE equivalent, key selection criteria include differential HCSL output compliance (0.7V, 100Ω), programmable PLL bandwidth, tristate control via SRC_STOP#/PWRDWN#, SMBus register access for per-output enable/disable, and industrial temperature support (–40°C to +85°C).

Technical Context

This device operates as a dual-mode clock distribution IC: in PLL mode it cleans and retimes PCIe reference clocks (95–105 MHz) with sub-70ps cycle-to-cycle jitter; in bypass mode it functions as a low-skew fanout buffer supporting up to 400 MHz input. It implements current-mode HCSL outputs with external IREF resistor (475Ω ±1%) setting nominal 13.9mA output current (6 × IREF).

Control is implemented via dedicated LVTTL pins (SRC_STOP#, PWRDWN#, OE[0:7], PLL/BYPASS#) and an SMBus slave interface (7-bit address 0x6E) supporting indexed block read/write for configuration registers-including output enable, PLL bandwidth, SRC_DIV#, and SRC_STOP# behavior-enabling dynamic power management and system-level clock gating.

Key Specifications

Pinout & Package

Package: 48-pin TSSOP (A), Pb-free and RoHS-compliant, 240-mil wide, JEDEC MO-153F/ED footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N551, PI6C20800SIAE uniquely balances native HCSL compatibility, industrial temperature rating, and SMBus configurability-making it optimal for Intel server platforms requiring drop-in replacement of PI6C410BS-derived timing trees without redesign.

Availability

PI6C20800SIAE is available at Aetrix Electronics and suitable for PCIe server backplanes, Intel chipset reference distribution, and industrial embedded carrier boards requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6C20800SIAE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, signal integrity, and interface ICs for computing and communications infrastructure.

PI6C20800SIAE belongs to Pericom's PCIe clock buffer product line, engineered specifically to meet Intel platform timing specifications-including skew, jitter, and HCSL electrical compliance-for server, storage, and embedded applications.

FAQ

What is the function of the IREF pin, and what resistor value is required?

The IREF pin sets the output current for all eight HCSL differential pairs using an external precision resistor. A 475Ω ±1% resistor is required to establish the nominal 2.32mA reference current, resulting in 13.9mA per output (6 × IREF). Deviations beyond ±1% tolerance cause proportional output current error, directly affecting voltage swing and signal integrity.

How does the SMBus interface operate, and what is its default address?

The SMBus interface is slave-only, using a fixed 7-bit address of 0x6E (1101110b). It supports indexed block read/write for four 8-bit registers controlling output enable, PLL mode, bandwidth, and SRC_STOP# behavior. No external pull-ups are needed-the internal 10kΩ pull-ups on SDA/SCLK meet SMBus specification requirements.

Can PI6C20800SIAE operate in both PLL and bypass modes simultaneously?

No-PLL/BYPASS# is a single-pin mode selector: logic LOW configures fanout (bypass) mode; logic HIGH selects PLL mode. The device cannot split outputs between modes. Mode selection affects all eight output pairs uniformly and determines whether input jitter is filtered (PLL) or passed through (bypass).

What is the power-down current consumption, and how is it measured?

In power-down mode (PWRDWN# = LOW), current drops to ≤12µA when all outputs are tristated, or ≤80µA when outputs remain driven. These values are measured at VDD = 3.465V, TA = 25°C, with all inputs held static and no switching activity-verified per Pericom's DC Electrical Characteristics table (datasheet page 8).