Diodes Incorporated PI6C20800SIVE

Overview

PI6C20800SIVE from Pericom Semiconductor is a PCIe® 1:8 HCSL differential clock buffer with PLL/fanout mode selection, 8 differential output pairs (OUT0–OUT7), <60ps output-to-output skew (industrial grade), and SMBus programmable control. It serves as a companion to PI6C410BS clock generators in Intel server chipset platforms for distributing SRC clocks with precise timing integrity.

For engineers reviewing the PI6C20800SIVE datasheet, PI6C20800SIVE pinout, PI6C20800SIVE application, or PI6C20800SIVE equivalent, key selection criteria include differential HCSL output compliance, industrial temperature support (−40°C to +85°C), PLL bandwidth programmability, SMBus-based tristate control, and 48-pin SSOP (V) packaging with Pb-free/Green compliance.

Technical Context

This device operates as a dual-mode clock distribution IC: in PLL mode it cleans phase jitter for PCIe 2.0 applications (additive RMS phase jitter <1 ps), while in bypass mode it supports input frequencies up to 400 MHz with sub-8 ns propagation delay variation. It accepts 0.7V differential SRC/SRC# inputs and delivers matched HCSL outputs with programmable current via external IREF resistor (475Ω ±1%).

Control is implemented through dedicated LVTTL pins (SRC_STOP#, PWRDWN#, OE[0:7], PLL/BYPASS#) and an SMBus interface supporting indexed block read/write at address 0x6E. The LOCK signal provides latched PLL lock status, and OE_INV enables global inversion of enable/power control logic.

Key Specifications

Pinout & Package

Package: 48-pin SSOP (V), 300-mil wide, Pb-free and RoHS-compliant (JEDEC MO-118 AA). Thermal and mechanical data available per Pericom PD-1401 Rev F.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8T49N241 and NB3N551, PI6C20800SIVE uniquely balances PCIe-specific jitter filtering, per-output SMBus control, industrial temperature range, and HCSL-only optimization-making it optimal for server-class PCIe clock trees where reliability and configurability outweigh multi-protocol needs.

Availability

PI6C20800SIVE is available at Aetrix Electronics and suitable for Intel server platform design, PCIe 2.0 switch fabric timing, and industrial embedded backplane applications requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6C20800SIVE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, interface, and signal-integrity solutions for computing and communications infrastructure.

The PI6C20800SIVE belongs to Pericom's PCIe-optimized clock buffer product line, designed specifically to meet Intel platform reference clock distribution requirements with HCSL compliance, low additive jitter, and industrial-grade reliability.

FAQ

What is the function of the IREF pin, and how is it configured?

The IREF pin sets the output current for all HCSL outputs via an external 475Ω ±1% resistor connected to VDD. This establishes a reference current (IREF = 2.32mA), and each output delivers 6×IREF = 13.9mA into a 100Ω differential load, ensuring 0.7V swing and compliance with PCIe HCSL specifications. No internal trimming is required.

How does the SMBus interface control output enable behavior?

The SMBus interface allows per-output enable/disable via Data Byte 1 (bits 0–7), where each bit corresponds to one output pair (OUT0–OUT7). Writing '0' disables that output (tristate), '1' enables it. This enables dynamic lane power management independent of the OE[0:7] pins, supporting advanced PCIe link power state transitions.

What is the difference between PI6C20800S and PI6C20800SIVE?

PI6C20800SIVE is the industrial-grade variant: it shares identical functionality and pinout with PI6C20800S but is characterized and qualified for −40°C to +85°C ambient operation. Its output skew is specified at ≤65ps (vs. ≤50ps for commercial-grade PI6C20800S), and AC parameters are guaranteed across the full industrial range.

Can PI6C20800SIVE operate without an external crystal or reference oscillator?

No. PI6C20800SIVE is a clock buffer-not a clock generator-and requires an external differential HCSL clock source (e.g., PI6C410BS) applied to SRC/SRC#. It has no internal oscillator or crystal input; its PLL only filters and redistributes the incoming reference, with no frequency synthesis capability.