Diodes Incorporated PI6C20800SIVEX

Overview

PI6C20800SIVEX from Pericom Semiconductor is a PCIe®-compliant 1:8 HCSL differential clock buffer with PLL/fanout mode selection, 8 differential output pairs (OUT0–OUT7), <50ps output-to-output skew (PI6C20800S variant), and SMBus-controlled tristate enable. It serves as a companion to PI6C410BS clock generators in Intel server chipset timing trees.

For engineers reviewing the PI6C20800SIVEX datasheet, PI6C20800SIVEX pinout, PI6C20800SIVEX application, or PI6C20800SIVEX equivalent, key selection criteria include differential output current programmability (via IREF), PLL bandwidth control (PLL_BW#), SRC_DIV# frequency division, and industrial-grade operation (-40°C to +85°C) enabled by the SI suffix.

Technical Context

This device operates in two primary modes: PLL-based jitter filtering (95–105 MHz input, <70ps cycle-to-cycle jitter) or low-latency fanout bypass (95–400 MHz). It supports 0.7V HCSL differential outputs with programmable drive strength via external 475Ω IREF resistor, delivering nominal 13.9mA per output pair (6 × IREF).

Control is implemented through dedicated LVTTL pins (SRC_STOP#, PWRDWN#, OE[0:7], OE_INV) and an SMBus interface (SCLK/SDA) for register-level configuration of PLL bandwidth, output enable states, and SRC_DIV# behavior. The LOCK signal provides latched PLL lock status indication.

Key Specifications

Pinout & Package

Package: 48-pin SSOP (V48), 300-mil wide, Pb-free and RoHS-compliant (JEDEC MO-118 AA). Pin pitch: 0.025", body width: 0.300".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe® clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N551, PI6C20800SIVEX uniquely combines per-output enable control, programmable PLL bandwidth, and industrial temperature support in a pin-compatible drop-in solution for Intel reference designs - making it optimal for PCIe® 2.0 server timing where flexibility and qualification assurance are critical.

Availability

PI6C20800SIVEX is available at Aetrix Electronics and suitable for enterprise server motherboards, PCIe® switch-based storage arrays, and Intel chipset reference designs requiring stable component supply, long-term lifecycle support, and industrial-grade thermal performance.

Supply support for PI6C20800SIVEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-speed timing, interface, and signal integrity ICs for computing and communications infrastructure.

The PI6C20800S belongs to Pericom's PCIe®-optimized clock buffer product line, designed specifically to meet Intel server platform timing specifications with minimal external components and full reference design compatibility.

FAQ

What is the function of the IREF pin, and how is it configured?

The IREF pin connects to an external 475Ω ±1% resistor to ground, setting the nominal reference current at 2.32mA. This current scales the HCSL output drive strength: each differential output pair delivers 6 × IREF = 13.9mA into a 100Ω differential load, ensuring compliant 0.7V swing and impedance matching with PCIe® receivers.

How does the PLL/BYPASS# pin affect timing performance?

When PLL/BYPASS# is LOW, the device operates in fanout mode with sub-6ns propagation delay and supports input frequencies up to 400MHz, but provides no jitter filtering. When HIGH, it engages the PLL for jitter attenuation (cycle-to-cycle jitter <70ps), locking to 95–105MHz inputs with typical lock time under 1ms and LOCK signal assertion.

Can PI6C20800SIVEX be used in commercial-temperature applications?

Yes - the "SI" in PI6C20800SIVEX denotes the industrial temperature grade (-40°C to +85°C), but it is fully backward-compatible with commercial-temperature (0°C to +70°C) designs. No derating or configuration changes are needed; the same electrical specifications apply across both ranges.

What happens to outputs when both SRC_STOP# and PWRDWN# are asserted?

Both signals force all eight differential outputs into high-impedance (tristate) mode. PWRDWN# additionally disables the PLL, reduces supply current to ≤12mA, and requires SCLK/SDA to be tristated. SRC_STOP# alone stops clocking while preserving PLL lock state and output drive capability upon deassertion.