Diodes Incorporated PI6C20800SVE

Overview

PI6C20800SVE from Pericom Semiconductor is a PCIe®-compliant 1:8 HCSL differential clock buffer with PLL/fanout mode selection, <50ps output skew (PI6C20800S), <70ps cycle-to-cycle jitter, and SMBus-controlled tristate outputs-designed as a companion to PI6C410BS for Intel server chipset clock distribution.

For engineers reviewing the PI6C20800SVE datasheet, PI6C20800SVE pinout, PI6C20800SVE application, or PI6C20800SVE equivalent, key selection criteria include differential HCSL output compliance, programmable PLL bandwidth, SRC_DIV# frequency division, SMBus-configurable OE control, and industrial-grade thermal operation up to +85°C.

Technical Context

This device operates in dual modes: PLL mode (95–105 MHz input, low additive jitter <1 ps RMS for PCIe 2.0) or bypass/fanout mode (95–400 MHz), with configurable PLL bandwidth via PLL_BW# and selectable input division by 2 when SRC_DIV# is asserted low.

It integrates an SMBus slave interface (7-bit address 0x6E) supporting indexed block read/write for register-level control of output enables, SRC_STOP#, PWRDWN#, and PLL/BYPASS selection-enabling dynamic power management and system-level clock gating without external logic.

Key Specifications

Pinout & Package

PI6C20800SVE uses a 48-pin SSOP (300-mil wide, package code V), Pb-free and RoHS-compliant, with separate analog (VDD_A/VSS_A) and digital (VDD/VSS) power domains and dedicated IREF pin for precise current-mode output calibration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT 8T49N241 and ON Semi NB3N502, PI6C20800SVE offers balanced programmability and PCIe-specific optimization: SMBus configurability enables runtime adaptation, while its dedicated HCSL drive and <50 ps skew meet server motherboard layout constraints better than general-purpose alternatives.

Availability

PI6C20800SVE is available at Aetrix Electronics and suitable for PCIe Gen2 server motherboards, multi-slot add-in card carriers, and Intel C600/C610 chipset platforms requiring stable component supply, long-term lifecycle support, and Pb-free compliance.

Supply support for PI6C20800SVE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity ICs for computing and communications infrastructure.

PI6C20800SVE belongs to Pericom's PCIe clock buffer product line, engineered specifically for low-jitter, low-skew fanout in Intel server chipset reference designs-prioritizing HCSL compliance, SMBus configurability, and thermal robustness over generic clock distribution.

FAQ

What is the function of the IREF pin on PI6C20800SVE?

The IREF pin connects to an external 475 Ω 1% resistor to set the reference current (IREF = 2.32 mA), which directly scales the 6× current-mode HCSL output drive strength. This ensures precise 0.7 V common-mode voltage and 100 Ω differential impedance into standard PCIe termination loads, maintaining signal integrity across process/voltage/temperature variations.

How does the LOCK signal behave during power-up and PLL locking?

The LOCK signal is an open-drain LVTTL output that remains low until the internal PLL achieves stable lock, then transitions high and latches. It stays asserted until power is cycled or PWRDWN# is asserted. This provides a hardware-observable, glitch-free indication for BIOS or FPGA logic to delay PCIe link initialization until clock stability is confirmed.

Can PI6C20800SVE operate without an external crystal or reference oscillator?

No. PI6C20800SVE is a clock buffer-not a clock generator-and requires an external differential HCSL reference clock (e.g., from PI6C410BS) applied to SRC/SRC#. It has no internal oscillator or crystal interface; its PLL only filters and redistributes the supplied input, with optional divide-by-2 via SRC_DIV#.

What is the maximum allowable capacitive load on each HCSL output pair?

Each OUT[n]/OUT[n]# pair is characterized for 2 pF total pin capacitance (including PCB trace and receiver input). Exceeding this degrades rise/fall times and increases jitter; the datasheet specifies Trise/Tfall limits (175–700 ps) and skew (≤50 ps) only under the defined test load (Rp = 49.9 Ω, Rs = 33 Ω, CL = 2 pF).