Diodes Incorporated PI6C20800VE

Overview

PI6C20800VE from Pericom Semiconductor is a high-speed, low-noise 1:8 differential clock driver IC designed as a companion to PI6C410B for Intel PCI Express® chipset clock distribution. It supports PLL mode (100–200 MHz) or bypass mode (100–400 MHz), delivers eight differential output pairs with <50 ps output-to-output skew and <50 ps cycle-to-cycle jitter, and features SMBus-controlled tristate outputs and programmable PLL bandwidth.

For engineers reviewing the PI6C20800VE datasheet, PI6C20800VE pinout, PI6C20800VE application, or PI6C20800VE equivalent, key selection criteria include differential output current control via IREF, dual-mode operation (PLL/fanout), SMBus-configurable output enables per channel, and dedicated power-down sequencing with LOCK status indication.

Technical Context

The PI6C20800VE operates as a current-mode differential clock buffer with 0.7V output swing and 100Ω differential termination support. Its PLL architecture supports frequency multiplication/division and lock detection via the LOCK pin, while bypass mode routes input directly to outputs with minimal added jitter.

Control is implemented through mixed-signal interfaces: asynchronous LVTTL inputs (SRC_STOP#, PWRDWN#, OE[0:7], PLL/BYPASS#) and synchronous SMBus (SCLK/SDA) for register-level configuration of output enables, SRC_DIV#, PLL bandwidth, and SRC_STOP# behavior - enabling dynamic reconfiguration without reset.

Key Specifications

Pinout & Package

PI6C20800VE is packaged in a Pb-free, green 48-pin SSOP (300-mil wide, package code V), compliant with JEDEC MO-118 AA outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar differential clock driver applications.

Compared with IDT8T49N242 and Si53302-D05, PI6C20800VE offers simpler integration with existing PI6C410B-based PCIe clock trees, lower latency in bypass mode, and direct LVTTL/SMBus control without external memory - making it optimal for cost-sensitive, high-volume PCIe platform designs where upstream clock synthesis is already implemented.

Availability

PI6C20800VE is available at Aetrix Electronics and suitable for PCIe root complexes, server backplanes, and embedded computing platforms requiring stable component supply and long-term industrial availability.

Supply support for PI6C20800VE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-performance timing, interface, and signal integrity solutions, acquired by Diodes Incorporated in 2016; its timing portfolio continues under Diodes' Precision Timing division.

The PI6C20800 belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically for low-skew, low-jitter distribution of reference clocks in multi-lane serial interconnect systems.

FAQ

What is the function of the IREF pin and how is it configured?

The IREF pin sets the nominal output current for all differential outputs via an external precision resistor. With a 475Ω 1% resistor connected to ground, IREF draws 2.32 mA from VDD, establishing a 13.9 mA (6×IREF) output drive current into a 100Ω differential load. This configuration ensures consistent 0.7V swing and matches PCIe receiver input thresholds.

How does the LOCK pin behave during power-up and PLL locking?

The LOCK pin is an open-drain LVTTL output that remains LOW until the internal PLL achieves stable lock, then transitions HIGH and latches in that state. It stays HIGH even if the input clock is temporarily lost, requiring power cycle or reset to clear. This latched behavior enables reliable firmware polling during PCIe initialization without missing the lock event.

Can PI6C20800VE operate without an external clock synthesizer like PI6C410B?

No - PI6C20800VE requires a differential SRC clock input (SRC/SRC#) and is explicitly designed as a companion device to PI6C410B. It lacks an integrated oscillator or crystal input; its PLL only conditions an externally supplied clock. For standalone operation, alternatives like IDT8T49N242 or Si53302-D05 are required.

What is the timing relationship between PWRDWN# assertion and output disable?

When PWRDWN# is asserted LOW, outputs transition to tristate within <300 µs and remain disabled until de-assertion. During this time, SCLK and SDA must also be tristated to prevent bus contention. After PWRDWN# is de-asserted, outputs stabilize within 1 ms, and the LOCK pin re-evaluates PLL lock status before enabling outputs - ensuring safe, glitch-free resumption.