Diodes Incorporated PI6C20800VEX

Overview

PI6C20800VEX from Pericom Semiconductor is a high-speed, low-noise 1:8 differential clock driver IC designed as a companion to PI6C410B for Intel PCI Express® chipset timing distribution. It delivers eight differential output pairs with <50ps output-to-output skew and <50ps cycle-to-cycle jitter in PLL mode (100–200 MHz) or bypass mode (100–400 MHz), operating at 3.3V. Its SMBus-controllable tristate outputs, programmable PLL bandwidth, and SRC_DIV# input enable flexible clock management in PCIe Gen1/Gen2 root complex and switch applications.

For engineers reviewing the PI6C20800VEX datasheet, PI6C20800VEX pinout, PI6C20800VEX application, or PI6C20800VEX equivalent, key selection criteria include differential output current accuracy (±12% @ IREF = 2.32 mA), dual-mode PLL/fanout operation, SMBus-indexed register control, and SSOP-48 (V) package compatibility with PCIe reference clock routing constraints.

Technical Context

The PI6C20800 operates in two distinct functional modes: PLL mode (100–200 MHz input, jitter-cleaning function) and bypass mode (100–400 MHz input, low-latency fanout). Mode selection is controlled by the PLL/BYPASS# pin, while PLL bandwidth (high/low) is set via PLL_BW#. The device supports SRC clock division-by-2 when SRC_DIV# is asserted low, enabling compatibility with 100 MHz PCIe reference sources.

All eight differential output pairs (OUT0–OUT7 with complementary # pins) use current-mode logic (CML) buffers with external IREF biasing (475Ω resistor), delivering nominal 0.7V differential swing into 100Ω loads. Output enable is individually configurable per channel via OE[0:7], with global control via SRC_STOP# and PWRDWN#, both active-low and optionally inverted by OE_INV.

Key Specifications

Pinout & Package

PI6C20800VEX is packaged in a Pb-free, green 48-pin SSOP (Package Code V, 300-mil width, JEDEC MO-118 AA), optimized for PCIe board layout with separate analog (VDD_A/VSS_A) and digital (VDD/VSS) power domains.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar differential clock distribution applications.

Compared with IDT 8T49N242 and ON Semi NB3N551, PI6C20800VEX offers unique value in PCIe Gen2-compliant jitter performance with minimal external components (only IREF resistor), SMBus configurability for dynamic power management, and native compatibility with PI6C410B-based timing architectures - making it optimal for mid-range server and embedded PCIe platforms requiring balance of precision, flexibility, and BOM simplicity.

Availability

PI6C20800VEX is available at Aetrix Electronics and suitable for PCIe root complex timing, PCIe switch clock distribution, and embedded storage controller clocking requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6C20800VEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-performance timing, interface, and signal-integrity solutions for computing and communications infrastructure.

The PI6C20800 belongs to Pericom's PCIe-optimized clock buffer product line, engineered specifically to meet Intel's platform timing specifications for Gen1/Gen2 root complexes and switches - emphasizing low skew, deterministic jitter, and seamless integration with PI6C410B synthesizers.

FAQ

What is the function of the IREF pin, and how is its value determined?

The IREF pin sets the output current for all eight differential drivers using an external 475 Ω 1% resistor connected to VDD, establishing a nominal 2.32 mA reference current. This directly determines the 0.7 V differential output swing into 100 Ω loads. Deviations in resistor tolerance or VDD variation cause proportional changes in output amplitude and edge rate, so tight resistor tolerance and stable 3.3 V supply are required for PCIe timing compliance.

How does the LOCK signal behave during PLL lock acquisition and loss?

The LOCK pin is an open-drain 3.3 V LVTTL output that transitions HIGH and latches when the PLL achieves stable lock (typically within 1 ms after PWRDWN# deassertion). It remains HIGH until the PLL loses lock due to input loss or excessive jitter, at which point it transitions LOW. This latched behavior provides a reliable hardware flag for BIOS or FPGA logic to confirm clock stability before PCIe link training begins.

Can PI6C20800VEX operate without an SMBus controller in the system?

Yes. SMBus is optional for configuration; default operation uses pin-strapped settings (e.g., PLL/BYPASS# and PLL_BW# pins hardwired). All outputs enable at power-up if OE[0:7] are HIGH, and PLL mode is active if PLL/BYPASS# is LOW. SMBus is only required for dynamic reconfiguration (e.g., changing bandwidth or disabling individual outputs during runtime) - not for basic PCIe clock distribution.

What is the recommended termination for the differential outputs?

The differential outputs require 100 Ω differential termination (e.g., 50 Ω to VTT on each leg, or a 100 Ω resistor across OUTn and OUTn#) per PCIe CML specification. The internal current-source design expects this load to generate the specified 0.7 V swing. Mismatched termination causes amplitude deviation and increased jitter; layout must maintain controlled 100 Ω differential impedance with <5 ps skew between complementary traces.