Diodes Incorporated PI6C21200AE

Overview

PI6C21200AE from Pericom Semiconductor is a 1:12 PCIe® differential clock buffer with HCSL-compatible signaling, supporting twelve 0.7V differential output pairs, <50ps output-to-output skew, <50ps cycle-to-cycle jitter, and programmable gear ratio for derivative frequency generation in Intel PCIe® chipset applications.

For engineers reviewing the PI6C21200AE datasheet, PI6C21200AE pinout, PI6C21200AE application, or PI6C21200AE equivalent, this device serves as a high-fidelity clock distribution companion to the PI6C410B synthesizer in server motherboard timing trees, requiring precise skew control, SMBus-configurable PLL/fan-out mode, and per-output tristate enable via dedicated OE# pins or register control.

Technical Context

The PI6C21200AE implements a dual-mode PLL architecture-configurable via SA_2/PLLBypass# pin or SMBus register (Byte 2, Bit 5)-enabling either low-jitter PLL-based multiplication or zero-delay fan-out operation. Its current-mode differential outputs deliver 0.7V amplitude into 100Ω differential loads with ±12% current accuracy referenced to IREF = 2.32mA.

Timing control is implemented through three hierarchical layers: hardware pin strapping (FS_A, HIGH_BW#, OE_[0:10]#), SMBus-addressed register access (7-bit slave address selectable via SA_[0:2]), and indexed block/byte read-write protocols supporting dynamic gear ratio reconfiguration (Bytes 0–1) and output enable state management (Bytes 1–2).

Key Specifications

Pinout & Package

Package: 56-pin, 240-mil wide TSSOP (A56), Pb-free and RoHS-compliant, 0.5mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe® clock distribution applications.

Compared with IDT 8T49N241 and ON Semi NB3N512, the PI6C21200AE uniquely balances programmable frequency synthesis support (via external PI6C410B), per-output tristate control, and PCIe®-specific HCSL drive-making it optimal for scalable, field-upgradable server timing architectures.

Availability

PI6C21200AE is available at Aetrix Electronics and suitable for server motherboard design, PCIe® switch timing distribution, Intel chipset companion clocking, and enterprise SSD controller clocking requiring stable component supply and long-term lifecycle support.

Supply support for PI6C21200AE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-speed timing, signal integrity, and interface solutions for datacenter and communications infrastructure.

The PI6C21200AE belongs to Pericom's PCIe®-optimized clock buffer product line, designed specifically to meet Intel's SRC interface specification and support scalable, low-skew clock distribution in multi-slot server platforms.

FAQ

What is the function of the FS_A pin on PI6C21200AE?

The FS_A pin is a 3.3V LVTTL input that latches at power-up to select the default gear ratio lookup table used by SMBus Byte 0. When FS_A = 0, the device defaults to ratios optimized for CPU input frequencies above 200MHz; when FS_A = 1, it selects ratios for frequencies at or below 200MHz. This enables automatic configuration matching Intel chipset reference designs without SMBus initialization.

How does the PI6C21200AE achieve <50ps output skew?

The PI6C21200AE achieves <50ps output-to-output skew through matched internal current-mode output buffers, symmetrical routing in the 56-pin TSSOP package, and dedicated ground/power planes (VSS/VSS_A separation). Skew is measured differentially across same-group outputs (e.g., OUT0–OUT9) under identical load conditions (100Ω diff, 2pF), per AC switching specs in PS8821B Rev 10/14/09.

Can the PI6C21200AE operate without an SMBus controller?

Yes. All critical functions-including output enable (via OE# pins), PLL/fan-out mode (via SA_2/PLLBypass#), and default gear ratio (via FS_A)-are controllable by hardware pins. SMBus is optional for dynamic reconfiguration (e.g., runtime gear ratio changes, register-based OE control, or PLL bandwidth adjustment) but not required for basic 1:1 clock distribution.

What is the role of the IREF pin and how is it configured?

The IREF pin connects to an external 475Ω 1% resistor to set the reference current (IREF = 2.32mA). This current defines the 6×IREF (≈13.9mA) output drive strength for all 12 differential pairs. The resistor must be placed close to the IREF pin with short traces to maintain current accuracy within ±12%, as specified in the DC electrical characteristics table.