Diodes Incorporated PI6C2410QE

Overview

PI6C2410QE from Pericom Semiconductor is a low-skew, low-jitter PLL-based clock buffer with selectable divider/multiplier functionality, designed specifically for PCI-X clock distribution in servers and workstations. It delivers four synchronous 3.3V CMOS outputs (OUT0–OUT3), supports dual input frequency ranges (10–40 MHz and 40–80 MHz via HF#), and features independent output enable control (OE0–OE3) with <150 ps phase error and <200 ps output skew.

For engineers reviewing the PI6C2410QE datasheet, PI6C2410QE pinout, PI6C2410QE application, or PI6C2410QE equivalent, this device is selected for high-reliability, low-EMI clock fanout in industrial-grade server platforms requiring precise timing synchronization, spread-spectrum compatibility, and thermal stability from –40°C to +85°C.

Technical Context

The PI6C2410QE integrates a PLL core with programmable feedback path selection (FBIN/FBOUT) and dual-range input detection (HF#), enabling stable lock across 10–80 MHz input frequencies. Its internal divider/multiplier logic (VID[1:0]) allows configurable output ratios relative to CLKIN, supporting both integer division and multiplication modes.

All four outputs are edge-aligned with sub-200 ps inter-output skew and <200 ps cycle-to-cycle jitter at 66.67 MHz (Cl = 15 pF). The device uses separate analog (AVCC/AGND) and digital (VCC/GND) supply domains to minimize noise coupling, and supports spread-spectrum clocking on CLKIN to reduce EMI without degrading timing integrity.

Key Specifications

Pinout & Package

PI6C2410QE is packaged in a 24-pin QSOP (Package Code Q), Pb-free and RoHS-compliant, with 0.635 mm lead pitch and 8.56 mm × 3.99 mm body dimensions. Pin 1 is marked by a beveled corner; the package supports standard surface-mount reflow profiles.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock buffer applications.

Compared with IDT 5V2310PGG and ON Semi NB3N511MNR2G, PI6C2410QE uniquely combines programmable frequency scaling, industrial temperature support, CMOS-compatible outputs with per-output enable, and spread-spectrum tolerance - making it the sole fit for upgradeable, EMI-constrained PCI-X server designs.

Availability

PI6C2410QE is available at Aetrix Electronics and suitable for PCI-X server backplanes, workstation memory subsystems, and industrial embedded control backplanes requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PI6C2410QE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-performance timing, interface, and signal-integrity solutions for computing and communications infrastructure.

The PI6C2410QE belongs to Pericom's PCI-X clock buffer product line, engineered to replace discrete oscillator+fanout solutions with integrated PLL-based timing that meets stringent skew, jitter, and EMI requirements of enterprise-class server platforms.

FAQ

What is the maximum supported output frequency for PI6C2410QE?

The PI6C2410QE supports output frequencies up to 133.33 MHz when configured in 2× multiplication mode with an 66.67 MHz input. This is verified in the datasheet's switching characteristics table (FOUT = 133.33 MHz, Cl = 15 pF), and aligns with PCI-X 133 MHz timing requirements. Output drive strength remains compliant within specified jitter and skew limits at this rate.

Can PI6C2410QE operate with a 2.5 V supply?

No. PI6C2410QE is specified exclusively for 3.3 V ±0.3 V operation (VCC and AVCC). The absolute maximum ratings show VCC up to 6.3 V, but DC electrical characteristics - including VOL/VOH thresholds and output drive - are characterized only at 3.3 V. Operation at 2.5 V violates the recommended operating conditions and risks functional failure or excessive jitter.

How does HF# pin selection affect PLL lock time?

HF# configures the PLL's internal loop filter bandwidth: LOW (40–80 MHz mode) uses a higher-bandwidth filter for faster lock (<10 ms typical), while HIGH (10–40 MHz mode) uses a lower-bandwidth filter for improved jitter suppression but longer lock time (~20 ms). This trade-off is documented in Pericom's application note AN-501 and confirmed in the device's lock-time characterization data.

Is FBOUT required to be connected for normal operation?

FBOUT is optional. When using internal feedback (default configuration), FBOUT is left unconnected and FBIN is tied to CLKIN or a divided version. FBOUT becomes necessary only in external feedback configurations - for example, when driving a remote PLL or when monitoring PLL output phase. The datasheet's block diagram and pin description confirm FBOUT is an output-only terminal with no mandatory connection.