Diodes Incorporated PI6C48535-01LEX

Overview

PI6C48535-01LEX from Diodes Incorporated (formerly Pericom) is a 3.3V low-skew 1-to-4 LVPECL fanout buffer with dual selectable single-ended inputs (CLK0/CLK1), four differential LVPECL output pairs, 500 MHz max frequency, 80 ps max output skew, and -40°C to +85°C operation. It enables LVTTL/LVCMOS-to-LVPECL clock translation in high-speed datacom backplanes.

For engineers reviewing the PI6C48535-01LEX datasheet, PI6C48535-01LEX pinout, PI6C48535-01LEX application, or PI6C48535-01LEX equivalent, key selection criteria include input-level compatibility (LVCMOS/LVTTL), LVPECL output drive capability, sub-100 ps output skew, additive jitter (36.7 fs typ.), and TSSOP-20 thermal/power performance under 3.3V supply.

Technical Context

The PI6C48535-01LEX implements asynchronous clock enable control via CLK_EN, synchronizing output assertion/deassertion to the next rising/falling edge of the selected input clock. Its dual-input multiplexer (CLK_SEL-controlled) supports dynamic source switching between CLK0 and CLK1 without glitching when CLK_EN is active.

Each of the four LVPECL output pairs (Q0/nQ0 through Q3/nQ3) delivers 0.6–1.0 Vpp swing into 50 Ω to VCC−2.0 V, with VOH = VCC−0.9 V and VOL = VCC−1.7 V. Input pins feature internal 50 kΩ pull-up (CLK_EN) or pull-down (CLK_SEL, CLK0, CLK1), eliminating external biasing components.

Key Specifications

Pinout & Package

Package: 20-pin Pb-free & Green TSSOP (L), 173-mil width, JEDEC MO-153 compliant, 0.65 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL fanout buffer applications.

Compared with ICS853S01I-01LF and SY89851UMG, the PI6C48535-01LEX uniquely combines dual-input selection, 500 MHz operation, and <80 ps skew-making it optimal for reconfigurable, high-bandwidth telecom clock trees where source agility and timing precision are co-constrained.

Availability

PI6C48535-01LEX is available at Aetrix Electronics and suitable for telecom line cards, data center switch fabrics, optical transport equipment, and high-speed test instrumentation requiring stable component supply and long-term lifecycle support.

Supply support for PI6C48535-01LEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated acquired Pericom Semiconductor in 2017, integrating its high-performance timing and interface portfolio into a broad analog and mixed-signal solutions provider.

The PI6C48535-01LEX belongs to Diodes' legacy Pericom timing product line, engineered specifically for low-skew clock distribution in datacom and telecom infrastructure where LVPECL signal integrity and multi-source flexibility are essential.

FAQ

What termination is required for the LVPECL outputs?

Each LVPECL output pair (e.g., Q0/nQ0) must be terminated with a 50 Ω resistor to VCC−2.0 V. This establishes the correct common-mode voltage (VCC−1.3 V) and ensures specified VOH/VOL levels and 0.6–1.0 Vpp swing. AC-coupling is not supported per datasheet design.

Can CLK_EN be toggled asynchronously while CLK0/CLK1 are running?

Yes. CLK_EN operates asynchronously and forces outputs low/high immediately, but output enable/disable transitions occur synchronously on the next rising or falling edge of the currently selected clock (CLK0 or CLK1), preventing runt pulses or metastability.

Is the PI6C48535-01LEX pin-compatible with earlier Pericom buffers like PI6C2405-01?

No. The PI6C48535-01LEX uses a 20-pin TSSOP with distinct pin assignments-including dual clock inputs, CLK_SEL, and three VCC pins-not found in the 16-pin SOIC package of PI6C2405-01. Layout redesign is required for replacement.

Does the device support spread-spectrum clocking (SSC) on its inputs?

No. The PI6C48535-01LEX is not characterized for SSC input tolerance. Its AC specifications-including jitter and skew-are validated only for fixed-frequency LVCMOS/LVTTL inputs. Applying SSC may violate timing margins and increase measured output jitter.