Diodes Incorporated PI6C48535-11BLIEX

Overview

PI6C48535-11BLIEX from Pericom Semiconductor is a 3.3V low-jitter 1-to-4 LVPECL fanout buffer with selectable crystal or LVCMOS/LVTTL input, 4 differential LVPECL output pairs, <0.05 ps typ additive phase jitter (156.25 MHz, 12 kHz–20 MHz), 1.5 ns max propagation delay, and operation from –40°C to +85°C. It serves as a clock translation and distribution device in high-speed serial data links.

For engineers reviewing the PI6C48535-11BLIEX datasheet, PI6C48535-11BLIEX pinout, PI6C48535-11BLIEX application, or PI6C48535-11BLIEX equivalent, key selection criteria include differential output skew (≤30 ps), part-to-part skew (≤200 ps), input compatibility (LVCMOS/LVTTL or fundamental-mode crystal), and 500 MHz maximum output frequency in telecom and datacom timing systems.

Technical Context

The PI6C48535-11BLIEX implements a single-input, four-output LVPECL fanout architecture with asynchronous CLK_EN control enabling synchronized output enable/disable on clock edges. Its dual-input path supports either crystal (Xtal1/Xtal2) or single-ended clock (CLK) via CLK_SEL, with internal 50 kΩ pull-down/pull-up resistors ensuring deterministic startup states.

It delivers rail-to-rail LVPECL outputs (VOH = 2.1–2.6 V, VOL = 1.3–1.8 V) with 0.6–1.1 V differential swing at 156.25 MHz, and meets stringent AC timing specs: 100–400 ps rise/fall time, 48–52% duty cycle, and ≤30 ps output-to-output skew under matched load and supply conditions.

Key Specifications

Pinout & Package

Package: 20-pin TSSOP (L), 173-mil wide, Pb-free & Green compliant, JEDEC MO-153F/AC outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL fanout buffer applications.

Compared with ICS8535-11I and PI6C48535-11BLE, the PI6C48535-11BLIEX offers identical timing performance but lower quiescent current and full Pb-free/Green compliance-making it optimal for new designs targeting industrial temperature range and long-term supply continuity.

Availability

PI6C48535-11BLIEX is available at Aetrix Electronics and suitable for 10G Ethernet line cards, Synchronous Ethernet equipment, and PCIe Gen3 switch fabric requiring stable component supply, consistent parametric performance, and industrial-temperature reliability.

Supply support for PI6C48535-11BLIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-performance timing, interface, and signal integrity solutions, acquired by Diodes Incorporated in 2016; its timing portfolio remains widely deployed in telecom and datacom infrastructure.

The PI6C48535 series belongs to Pericom's low-jitter clock fanout buffer product line, designed specifically for high-speed serial interface clock distribution in telecom, enterprise networking, and storage systems where sub-100 fs jitter and sub-50 ps skew are critical.

FAQ

Does PI6C48535-11BLIEX require external termination resistors for LVPECL outputs?

No. The device integrates internal termination for LVPECL outputs and is designed to drive 50 Ω differential loads directly. External 50 Ω terminations to VEE are not required, reducing component count and layout complexity compared to discrete LVPECL drivers.

Can PI6C48535-11BLIEX accept a 25 MHz crystal and generate 125 MHz LVPECL outputs?

No. This device is a fanout buffer-not a frequency multiplier. It passes through or distributes the input frequency unchanged. A 25 MHz crystal input yields 25 MHz LVPECL outputs; frequency synthesis requires a PLL-based clock generator such as the PI6CG330xx series.

What is the recommended power supply decoupling for PI6C48535-11BLIEX?

Use one 100 nF X7R ceramic capacitor per VDD pin (Pins 10, 13, 18), placed within 2 mm of each pin and connected to a solid ground plane. Add a bulk 4.7 µF tantalum or polymer capacitor near the device to suppress low-frequency supply ripple.

Is PI6C48535-11BLIEX compatible with 2.5 V LVDS inputs?

No. The CLK input accepts only LVCMOS or LVTTL levels (VIH ≥2 V, VIL ≤0.8 V). It does not support LVDS, HCSL, or CML inputs. For 2.5 V differential inputs, consider the PI6C49515 or PI6C49115 family with integrated differential receivers.