Diodes Incorporated PI6C49018ZDIEX

Overview

PI6C49018ZDIEX from Pericom is a low-power, SMBus-programmable clock generator for PCI Express Gen1/Gen2 and Gigabit Ethernet systems. It delivers four 100 MHz differential HCSL outputs with -0.5% down spread, one 125 MHz 2.5 V CMOS output for Ethernet PHY timing, one 66.66 MHz CMOS output, and one 80 MHz CMOS output with selectable spread spectrum (–0.5%, –0.75%, or –1%). Designed for industrial temperature range (–40°C to +85°C) in a 40-pin TQFN package.

For engineers reviewing the PI6C49018ZDIEX datasheet, PI6C49018ZDIEX pinout, PI6C49018ZDIEX application, or PI6C49018ZDIEX equivalent, key selection considerations include its quad 100 MHz HCSL PCIe clock capability with integrated spread spectrum, independent output enable control via SMBus or PD_RESET, and dual-supply operation (3.3 V core / 2.5 V I/O).

Technical Context

The PI6C49018ZDIEX integrates a PLL-based clock synthesis architecture fed by a 25 MHz crystal input, generating synchronized low-jitter outputs across multiple domains. Its four 100 MHz HCSL outputs meet PCIe Gen1 jitter requirements (TJø ≤ 86 ps, TCC ≤ 150 ps), while the 125 MHz LVCMOS output complies with IEEE 802.3-2008 Gigabit Ethernet timing at 2.5 V.

SMBus interface enables dynamic configuration of spread spectrum (SS1/SS0 bits), individual output enables (OE bits per Byte 0–3), and hardware/software reset control (Byte 0 Bit 6/5). The device supports tri-state control on all single-ended outputs with weak pull-downs and features dedicated VDDO (2.5 V) and VDDX (oscillator supply) rails for optimized signal integrity.

Key Specifications

Pinout & Package

PI6C49018ZDIEX is housed in a 40-pin Thin Quad Flat No-Lead (TQFN) package with exposed thermal pad, optimized for high-density PCB layouts and thermal dissipation in networking and server applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with IDT8T49N242A and Si53320-D-GM, the PI6C49018ZDIEX provides purpose-built HCSL drive strength and PCIe-optimized jitter performance at lower cost and complexity, making it optimal for Gen1/Gen2 PCIe and Ethernet co-timing where fixed-frequency outputs suffice.

Availability

PI6C49018ZDIEX is available at Aetrix Electronics and suitable for PCI Express server motherboards, Gigabit Ethernet switch designs, industrial embedded gateways, and telecom line cards requiring stable component supply and long-term lifecycle support.

Supply support for PI6C49018ZDIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor was a fabless provider of high-performance timing, interface, and signal integrity solutions, acquired by Diodes Incorporated in 2016. Known for low-jitter clock generators and PCIe-compliant devices targeting networking and computing infrastructure.

The PI6C49018 belongs to Pericom's low-power networking clock generator product line, designed specifically to replace discrete crystal oscillators and buffer ICs in space-constrained, thermally demanding PCIe and Ethernet applications.

FAQ

What is the default spread spectrum setting for the 100 MHz PCIe outputs?

The default spread spectrum setting for all four 100 MHz PCIe outputs is –0.5% down spread, enabled at power-up. This is hardwired in the device's internal configuration and cannot be disabled via SMBus - only the 80 MHz output's spread spectrum is fully programmable (–0.5%, –0.75%, or –1%).

Can the 125 MHz output operate at 3.3 V instead of 2.5 V?

No - the 125 MHz output is electrically specified only for VDDO = 2.5 V, with VOH = 2.4 V (min) at IOH = –8 mA and VOL = 0.4 V (max) at IOL = 8 mA. Driving it at 3.3 V violates absolute maximum ratings and risks latch-up or degraded jitter performance.

How does PD_RESET interact with SMBus-controlled output enables?

When PD_RESET is pulled low, it overrides all SMBus OE settings: all outputs are tri-stated, PLLs are powered down, and SMBus registers revert to power-on defaults. After PD_RESET deassertion, SMBus retains control unless Byte 0 Bit 6 is set to hardware mode (Bit 6 = 0), which disables software OE control entirely.

Is the 60 MHz output functional without SMBus configuration?

Yes - the 60 MHz output is enabled by default (Byte 3 Bit 7 = 0 at power-up), but its frequency accuracy depends on the 25 MHz crystal reference and internal divider chain. It requires no SMBus initialization to function, though spread spectrum and OE control for this output are SMBus-accessible via Byte 3.