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Diodes Incorporated PI6C4911506-06LIEX

Part No.:
PI6C4911506-06LIEX
Manufacturer:
Diodes Incorporated
Category:
Clock Buffers, Drivers
Package:
24-TSSOP (0.173", 4.40mm Width)
Datasheet:
AetrixPI6C4911506-06LIEX.pdf
Description:
IC CLK BUFFER 1:6 1.5GHZ 24TSSOP
Quantity:
Payment:
Payment
Shipping:
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Inventory:2,546

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Product details

Overview

PI6C4911506-06LIEX from Diodes Incorporated is a low-skew, 1-to-6 LVPECL fanout buffer supporting crystal, LVCMOS, and differential clock inputs with up to 1.5 GHz output frequency, <0.03 ps typical additive jitter (12 kHz–20 MHz), and 1.5 ns typical propagation delay. It delivers six differential LVPECL output pairs for high-speed clock distribution in telecom infrastructure and FPGA timing systems.

For engineers reviewing the PI6C4911506-06LIEX datasheet, PI6C4911506-06LIEX pinout, PI6C4911506-06LIEX application, or PI6C4911506-06LIEX equivalent, key selection criteria include input flexibility (XTAL/LVCMOS/differential), industrial temperature range (−40°C to +85°C), TSSOP-24 package compatibility, and sub-80 ps output skew under matched load conditions.

Technical Context

This device integrates a configurable input multiplexer selecting among XTAL_IN/XTAL_OUT, single-ended CLK0, or differential CLK1/nCLK1, with independent CLK_EN and dual CLK_SEL pins enabling dynamic source switching. Internal termination resistors (51 kΩ pulldown on CLK0/CLK1, 51 kΩ pullup on nCLK1) simplify board-level interface design.

It operates from dual supply rails (VDD = 2.5 V or 3.3 V, VEE = 0 V), supports level-shifted I/O via separate VDD/VEE domains, and maintains <0.03 ps RMS additive jitter at 156.25 MHz with 12 kHz–20 MHz integration-critical for SerDes and PCIe Gen4+ clocking.

Key Specifications

ParameterValue and Actual Design Meaning
Output Count6 differential LVPECL output pairs (Q0–Q5 / nQ0–nQ5)
Max Output Frequency1.5 GHz (differential input); enables 10G/25G Ethernet PHY clocking
Additive Phase Jitter<0.03 ps RMS (156.25 MHz, 12 kHz–20 MHz) - meets SONET OC-192 and CPRI jitter budgets
Propagation Delay1.5 ns typ. (input crossing point to output crossing point) - ensures deterministic timing across multi-FPGA systems
Output Skew<80 ps max between outputs - preserves phase alignment across parallel data lanes
Supply Voltage2.5 V or 3.3 V core (VDD), 0 V negative rail (VEE) - supports mixed-voltage system integration
Operating Temp−40°C to +85°C - qualified for industrial-grade base station and networking equipment

Pinout & Package

Package: 24-pin TSSOP (173 mil wide), RoHS-compliant, tape-and-reel (X suffix).

Pin/TerminalCircuit RoleDesign Meaning
1, 2 (nQ2, Q2)Differential LVPECL output pairProvides one of six synchronized clock outputs; requires 100 Ω differential termination
3, 19, 22 (VDD)Core power supplyAccepts 2.5 V or 3.3 V; decoupling required per pin for jitter suppression
4, 5 (nQ1, Q1)Differential LVPECL output pairSecond output channel; matched routing critical for skew control
6 (VEE)Negative supply referenceGround-referenced (0 V); establishes LVPECL common-mode baseline
7, 8 (nQ0, Q0)Differential LVPECL output pairPrimary output pair; often used for system master clock distribution
9, 16 (CLK_SEL0, CLK_SEL1)Input source select controlLVCMOS/LVTTL logic inputs defining active clock source per Table 3B
10 (XTAL_IN)Crystal oscillator inputDrives parallel-resonant fundamental-mode crystals (12–40 MHz, ESR ≤50 Ω)
11 (XTAL_OUT)Crystal oscillator outputCompletes Pierce oscillator circuit; connects to crystal's second terminal
12 (CLK_EN)Global clock enableActive-high; disables all outputs when LOW (high-impedance state not supported)
13 (CLK0)Single-ended clock inputLVCMOS/LVTTL-compatible; internal 51 kΩ pulldown resistor
14, 15 (CLK1, nCLK1)Differential clock inputLVDS/LVPECL-compatible; nCLK1 has internal 51 kΩ pullup, CLK1 pulldown
17, 18 (nQ5, Q5)Differential LVPECL output pairSixth output; routed with matched length to maintain skew <80 ps
20, 21 (nQ4, Q4)Differential LVPECL output pairFourth output; shares VDD pin 19 for localized power integrity
23, 24 (nQ3, Q3)Differential LVPECL output pairFifth output; adjacent to CLK_SEL1 (pin 16) for compact control layout

Key Features

FeatureDesign Value
Selectable reference inputsSupports crystal (12–40 MHz), single-ended LVCMOS (CLK0), or differential (CLK1/nCLK1) sources without external level-shifting
Ultra-low additive jitter<0.03 ps RMS enables compliance with stringent SerDes jitter masks (e.g., IEEE 802.3bj)
Low inter-output skew<80 ps max ensures simultaneous sampling across multi-lane interfaces like DDR5 memory controllers
Separate input/output supply domainVDD powers logic and outputs; no dedicated input supply needed - simplifies PCB power tree
Industrial temperature operationValidated from −40°C to +85°C - suitable for outdoor wireless baseband units and industrial PLCs

Applications

10G/25G Ethernet PHY ClockingFPGA Multi-Clock Domain Distribution

Use Scenario: Distributing a single low-jitter reference clock to multiple 10G/25G Ethernet PHY devices in a switch line card.

IC Role / Device Role / Timing Role: Fanout buffer providing six synchronized LVPECL clock outputs with sub-80 ps skew and <0.03 ps jitter.

Use Value: Enables deterministic inter-PHY timing alignment required for IEEE 802.3by KR4 FEC and PAM4 signaling.

Use Scenario: Driving clock inputs of multiple FPGAs (e.g., Xilinx Versal, Intel Agilex) sharing a common reference in a high-performance compute blade.

IC Role / Device Role / Timing Role: Low-skew LVPECL fanout buffer with selectable input sources (XTAL, differential, or LVCMOS).

Use Value: Eliminates need for discrete clock trees; maintains <1.5 ns propagation delay consistency across all outputs.

CPRI/O-RAN Radio Unit TimingPCIe Gen4/Gen5 Root Complex Clocking

Use Scenario: Generating synchronized clocks for multiple ADC/DAC channels and digital front-end processors in an O-RAN radio unit.

IC Role / Device Role / Timing Role: Industrial-temperature LVPECL buffer accepting crystal or differential inputs with ultra-low additive jitter.

Use Value: Meets CPRI Option 7/8 jitter requirements (<0.1 ps RMS) when cascaded with low-noise oscillators.

Use Scenario: Providing clean, low-skew clocks to PCIe Gen4/Gen5 root complex and endpoint devices in server motherboard designs.

IC Role / Device Role / Timing Role: 1.5 GHz-capable LVPECL fanout buffer with 1.5 ns tPD and 2.5 V/3.3 V supply flexibility.

Use Value: Supports PCIe reference clock specifications (100 MHz ±300 ppm, <1.0 ps RMS jitter) without additional cleanup ICs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL fanout buffer applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
ICS853S01I-41LF5-output LVPECL buffer; max 1.2 GHz; 0.05 ps jitter (12 kHz–20 MHz); no crystal input supportLacks XTAL_IN/XTAL_OUT pins - requires external oscillator for crystal-based designsChoose when only differential/LVCMOS inputs are needed and 5 outputs suffice
PI6C20400LE4-output LVPECL buffer; max 1 GHz; 0.07 ps jitter; supports crystal input but no CLK_SEL pinsNo dynamic input selection - fixed crystal-only operation limits flexibility in multi-source systemsPrefer for cost-sensitive, crystal-only applications where 4 outputs and lower frequency are acceptable

Compared with ICS853S01I-41LF and PI6C20400LE, the PI6C4911506-06LIEX uniquely combines 6 LVPECL outputs, 1.5 GHz capability, crystal/differential/LVCMOS input selection, and <0.03 ps jitter - making it optimal for high-density, multi-protocol timing architectures requiring minimal BOM count and maximum signal integrity.

Availability

PI6C4911506-06LIEX is available at Aetrix Electronics and suitable for 10G/25G Ethernet PHY clocking, FPGA multi-clock domain distribution, CPRI/O-RAN radio unit timing, and PCIe Gen4/Gen5 root complex clocking requiring stable component supply across extended temperature ranges.

Supply support for PI6C4911506-06LIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6C4911506-06LIEX belongs to Diodes' Precision Timing family, engineered specifically for low-jitter clock distribution in high-speed serial interfaces and multi-processor synchronization systems.

FAQ

What input types does the PI6C4911506-06LIEX support?

The device supports three input configurations: parallel-resonant crystal (12–40 MHz) via XTAL_IN/XTAL_OUT, single-ended LVCMOS/LVTTL (CLK0), and differential (CLK1/nCLK1). Input selection is controlled by CLK_SEL0 and CLK_SEL1 pins per the Configuration Table on page 6 of the datasheet. No external level shifters or buffers are required for any mode.

Does the PI6C4911506-06LIEX require external termination resistors for LVPECL outputs?

Yes - each differential LVPECL output pair (e.g., Q0/nQ0) requires a 100 Ω Thevenin termination to VDD − 2 V (typically implemented as two 50 Ω resistors: one to VDD − 2 V, one to ground). This matches standard LVPECL load requirements and ensures signal integrity at frequencies up to 1.5 GHz.

Can the PI6C4911506-06LIEX operate with only a 2.5 V supply?

Yes - the device is fully specified for VDD = 2.5 V ±5% (2.375 V to 2.625 V) across the full −40°C to +85°C operating range. All AC and DC parameters, including 1.5 GHz max output frequency and <0.03 ps jitter, are guaranteed at 2.5 V, enabling compatibility with low-voltage FPGA and ASIC power domains.

Is there a version of this part with different temperature grading or packaging?

Yes - the base part PI6C4911506-06LIE is identical except supplied in cut-tape (not tape-and-reel), while PI6C4911506-06ZHEX offers extended temperature (−40°C to +105°C) in TSSOP-24. No automotive-grade (AEC-Q100) variant exists for this specific part number.

PI6C4911506-06LIEX Specifications

Product attributes
Attribute value
Manufacturer:
Diodes Incorporated
Series:
-
Package/Case:
24-TSSOP (0.173", 4.40mm Width)
Packaging:
Tape & Reel (TR)
Product Status:
Active
Type:
Fanout Buffer (Distribution)
Number of Circuits:
1
Ratio - Input:Output:
1:6
Differential - Input:Output:
Yes/Yes
Input:
LVCMOS, LVTTL, Crystal
Output:
LVPECL
Frequency - Max:
1.5 GHz
Voltage - Supply:
2.375V ~ 2.625V, 3.135V ~ 3.465V
Operating Temperature:
-40°C ~ 85°C (TA)
Mounting Type:
Surface Mount
Grade:
-
Qualification:
-
Supplier Device Package:
24-TSSOP

PI6C4911506-06LIEX FAQ

1.How can I place an order for PI6C4911506-06LIEX through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6C4911506-06LIEX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6C4911506-06LIEX reliable?

The price and inventory of PI6C4911506-06LIEX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6C4911506-06LIEX is usually 5 days.

3.What payment methods are accepted for PI6C4911506-06LIEX?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6C4911506-06LIEX transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6C4911506-06LIEX?

PI6C4911506-06LIEX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6C4911506-06LIEX order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6C4911506-06LIEX?

For technical support, including PI6C4911506-06LIEX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6C4911506-06LIEX requirements.

6.How does Aetrix verify that PI6C4911506-06LIEX is sourced from the original manufacturer or authorized distributors?

All PI6C4911506-06LIEX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6C4911506-06LIEX meets industry standards.

7.What is the process for return or replacement of PI6C4911506-06LIEX?

All PI6C4911506-06LIEX units undergo pre-shipment inspection (PSI). If there is an issue with PI6C4911506-06LIEX, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6C4911506-06LIEX part is unused and in its original packaging.

Return procedure for PI6C4911506-06LIEX:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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