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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Buffers, Drivers

Diodes Incorporated PI6C49S1504LIE

Name: PI6C49S1504LIE
Brand: Diodes Incorporated
SKU: PI6C49S1504LIE
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PI6C49S1504LIE

Manufacturer:: Diodes Incorporated

Category:: Clock Buffers, Drivers

Package:: 28-TSSOP (0.173", 4.40mm Width)

Datasheet:: PI6C49S1504LIE.pdf

Description:: IC CLK BUFFER 3:4 1.5GHZ 28TSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

PI6C49S1504LIE from Diodes Incorporated is a high-performance 1:4 differential fanout buffer with two configurable output banks, supporting LVDS/LVPECL/HCSL signaling per bank, up to 1.5 GHz differential output frequency, <0.03 ps typical additive phase jitter (12 kHz–20 MHz), and industrial temperature range (−40°C to +85°C); used for low-jitter clock distribution in telecom backplanes and network switches.

For engineers reviewing the PI6C49S1504LIE datasheet, PI6C49S1504LIE pinout, PI6C49S1504LIE application, or PI6C49S1504LIE equivalent, key selection considerations include differential output bank configuration (OPMODEA/B), reference input selection (CLK_SEL[1:0]), synchronous output enable (Sync_OE), and dual-supply level-shifting capability (VDD/VDDO).

Technical Context

This device implements a dual-bank, user-selectable fanout architecture with independent mode control for Bank A (QA[0:1], QB[0:1]) and Bank B (QA[0:1], QB[0:1]) via OPMODEA[1:0] and OPMODEB[1:0]. Input selection between differential CLK0/CLK1 or crystal (Xtal_In/Xtal_Out) is managed by CLK_SEL[1:0].

The buffer features ultra-low skew (<40 ps within bank), sub-1.5 ns typical propagation delay, and separate VDD (core) and VDDO (output) supplies enabling level shifting across 2.5 V/3.3 V domains. IREF pin sets differential output current via external 475 Ω resistor.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & banks	4 differential outputs (2 per bank: QA/QB × 2 banks)
Max differential output frequency	1.5 GHz - supports 10G/25G SerDes clock distribution
Additive phase jitter (12 kHz–20 MHz)	<0.03 ps typ - meets stringent OC-192/SONET and PCIe Gen4 timing budgets
Output skew within bank	<40 ps - ensures tight timing alignment across parallel data paths
Propagation delay	<1.5 ns typ - enables precise system-level clock-to-data alignment
Supply voltages	VDD = 2.375–3.465 V (core), VDDO = 2.375–3.465 V (outputs) - supports mixed-voltage board design
Operating temperature	−40°C to +85°C - qualified for industrial-grade networking hardware

Pinout & Package

Package: 28-pin TSSOP (173 mil wide, RoHS-compliant, Pb-free "E" suffix).

Pin/Terminal	Circuit Role	Design Meaning
1 VEE	Power	Negative supply rail for differential output stage (tied to GND for single-ended operation)
3,4 CLK_SEL0/CLK_SEL1	Input	Selects reference source: Xtal, CLK0, or CLK1 - enables flexible clock tree topology
5,6 CLK0/nCLK0	Input	Differential clock input pair for Bank A - accepts LVPECL/LVDS/HCSL-compatible signals
7,8 CLK1/nCLK1	Input	Differential clock input pair for Bank B - supports redundant or alternate clock domain
9,10 Xtal_In/Xtal_Out	Input/Output	Crystal oscillator interface - allows internal crystal drive without external oscillator IC
11 Sync_OE	Input	Synchronous enable for Ref_Out - avoids glitches during clock switching
12 IREF	Output	Current-setting node - connects to 475 Ω resistor to calibrate differential output amplitude
14,15 nQB1/QB1	Output	Differential output pair for Bank B - independently configurable signal standard
19,20 nQB0/QB0	Output	Differential output pair for Bank A - matches QA[0:1] timing and skew characteristics
21 Ref_Out	Output	LVCMOS reference clock output (≤200 MHz) - provides system reset or auxiliary timing signal
22,23 nQA1/QA1	Output	Differential output pair for Bank A - shares same bank timing domain as QA0/QB0
27,28 nQA0/QA0	Output	Differential output pair for Bank A - primary output channel with lowest skew path

Key Features

Feature	Design Value
User-configurable output signaling per bank	LVPECL / LVDS / HCSL selectable via OPMODEA/B pins - eliminates need for external level translators
Ultra-low additive phase jitter	<0.03 ps RMS (156.25 MHz, 12 kHz–20 MHz) - preserves signal integrity in high-speed serial links
Low inter-output skew within bank	<40 ps - critical for parallel bus synchronization (e.g., DDR, QDR, XAUI)
Separate core and output supplies	VDD (core) and VDDO (outputs) - enables level shifting between 2.5 V logic and 3.3 V I/O domains
Integrated crystal driver	Xtal_In/Xtal_Out pins support fundamental-mode crystals - reduces BOM count vs. external XO

Applications

10G Ethernet Switch Fabric

PCIe Gen4 Clock Distribution

Use Scenario: Distributing low-jitter 156.25 MHz reference clocks to multiple SerDes lanes in Layer 3 switches.

IC Role / Device Role / Timing Role: Fanout buffer with bank-isolated LVPECL outputs driving 10G PHYs and MAC controllers.

Use Value: Sub-40 ps intra-bank skew ensures deterministic lane-to-lane deskew; <0.03 ps jitter maintains BER <1e−12 at 10.3125 Gbps.

Use Scenario: Splitting 100 MHz PCIe reference clock to four root complex endpoints with matched trace lengths.

IC Role / Device Role / Timing Role: Low-skew, low-jitter 1:4 fanout buffer operating in LVDS mode for noise-sensitive motherboard routing.

Use Value: Dual-supply architecture (VDD=2.5 V, VDDO=3.3 V) interfaces cleanly with mixed-voltage PCIe slots while meeting PCIe Gen4 jitter spec (1.0 ps RMS).

Optical Transport Network (OTN) Line Cards

High-Frequency Data Acquisition Systems

Use Scenario: Driving multiple framers and forward error correction (FEC) ASICs in 100G OTU4 line cards requiring 155.52 MHz sync.

IC Role / Device Role / Timing Role: Dual-bank buffer delivering LVDS clocks to FEC and mapping logic, and LVPECL clocks to serializer/deserializer chips.

Use Value: Independent bank configuration avoids signal standard conversion ICs; industrial temp rating ensures reliability in sealed chassis.

Use Scenario: Synchronizing ADC sampling clocks across four 16-bit, 250 MSPS analog front-ends in radar signal processing.

IC Role / Device Role / Timing Role: Ultra-low-jitter fanout buffer generating matched 250 MHz clocks in HCSL mode for ECL-compatible ADC inputs.

Use Value: 0.03 ps additive jitter contributes <0.005° phase error at 250 MHz - preserves ENOB >14.5 bits in coherent sampling systems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar differential fanout buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT8T49N242A	Integrated PLL with jitter cleaning; fixed LVDS outputs; no crystal driver	Requires external reference; suited for jitter-cleansing, not pure fanout	Choose when input clock has high jitter and system requires regeneration
Si53302-A01AGM	2:8 fanout; only LVDS outputs; no HCSL/LVPECL support; higher power (120 mA)	Lacks multi-standard flexibility; better for cost-sensitive LVDS-only designs	Choose when scaling to >4 outputs and HCSL/LVPECL compatibility is unnecessary

Compared with IDT8T49N242A and Si53302-A01AGM, PI6C49S1504LIE uniquely combines dual-bank signal standard selection, integrated crystal drive, and sub-40 ps skew - making it optimal for compact, multi-standard clock trees where BOM reduction and layout simplicity are prioritized over jitter cleaning or output count scaling.

Availability

PI6C49S1504LIE is available at Aetrix Electronics and suitable for 10G Ethernet switch fabric, PCIe Gen4 clock distribution, optical transport network line cards, and high-frequency data acquisition systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for PI6C49S1504LIE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance timing, power management, and signal integrity solutions for industrial, computing, and communications markets.

PI6C49S1504LIE belongs to Diodes' Pericom-branded high-speed clock buffer product line, designed specifically for low-jitter, multi-standard clock distribution in next-generation networking and data center infrastructure.

FAQ

What reference input configurations does PI6C49S1504LIE support?

The device supports three reference input sources selected via CLK_SEL[1:0]: single-ended or differential clock on CLK0/nCLK0, differential clock on CLK1/nCLK1, or fundamental-mode crystal connected to Xtal_In/Xtal_Out. Crystal drive capability eliminates need for external oscillator, reducing system component count and board space.

How is output signaling standard selected for each bank?

Bank A (QA/QB outputs) and Bank B (QA/QB outputs) are independently configured using OPMODEA[1:0] and OPMODEB[1:0] pins. Each 2-bit code selects LVPECL (00), LVDS (01), HCSL (10), or Hi-Z (11). This enables simultaneous delivery of different signal standards to heterogeneous downstream devices without level-shifting components.

What is the function of the IREF pin and how is it used?

IREF is a current-sense output pin that sets differential output amplitude by connecting an external 475 Ω ±1% resistor to ground. This resistor establishes nominal 15 mA output current, ensuring consistent voltage swing (e.g., 0.5 V for LVDS, 0.8 V for LVPECL) across process/voltage/temperature variations without trimming or calibration.

Does PI6C49S1504LIE support synchronous output enable, and how is it implemented?

Yes - Sync_OE pin enables synchronous gating of the Ref_Out signal only (not differential outputs). When Sync_OE = 0, Ref_Out enters high-impedance state; when Sync_OE = 1, Ref_Out drives LVCMOS output. This prevents metastability or glitches during clock source switching, preserving system-level timing integrity.

PI6C49S1504LIE Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: -

Package/Case:: 28-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Active

Type:: Fanout Buffer (Distribution), Multiplexer

Number of Circuits:: 1

Ratio - Input:Output:: 3:4

Differential - Input:Output:: Yes/Yes

Input:: Clock, Crystal

Output:: HCSL, LVDS, LVPECL

Frequency - Max:: 1.5 GHz

Voltage - Supply:: 2.375V ~ 3.465V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 28-TSSOP

PI6C49S1504LIE FAQ

1.How can I place an order for PI6C49S1504LIE through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6C49S1504LIE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6C49S1504LIE reliable?

The price and inventory of PI6C49S1504LIE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6C49S1504LIE is usually 5 days.

3.What payment methods are accepted for PI6C49S1504LIE?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6C49S1504LIE transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6C49S1504LIE?

PI6C49S1504LIE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6C49S1504LIE order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6C49S1504LIE?

For technical support, including PI6C49S1504LIE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6C49S1504LIE requirements.

6.How does Aetrix verify that PI6C49S1504LIE is sourced from the original manufacturer or authorized distributors?

All PI6C49S1504LIE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6C49S1504LIE meets industry standards.

7.What is the process for return or replacement of PI6C49S1504LIE?

All PI6C49S1504LIE units undergo pre-shipment inspection (PSI). If there is an issue with PI6C49S1504LIE, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6C49S1504LIE part is unused and in its original packaging.

Return procedure for PI6C49S1504LIE:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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