Diodes Incorporated PI6C557-01BQZHIEX

Overview

PI6C557-01BQZHIEX from Diodes Incorporated (acquired Pericom) is a PCIe 3.0-compliant spread spectrum clock generator that accepts a 25 MHz crystal or clock input and delivers one pair of HCSL differential outputs at 100 MHz with selectable -0.5% spread or no spread. It operates from 3.3 V ±10%, supports industrial temperature range (-40°C to +85°C), and targets EMI reduction in high-speed PC and embedded timing systems.

For engineers reviewing the PI6C557-01BQZHIEX datasheet, PI6C557-01BQZHIEX pinout, PI6C557-01BQZHIEX application, or PI6C557-01BQZHIEX equivalent, key selection criteria include PCIe 3.0 RMS jitter compliance (≤3 ps at 100 MHz), HCSL output drive capability (6×IREF, 2.32 mA typical), spread selection via SS1 pin, IREF precision resistor interface, and TQFN-16 package thermal performance (θJA = 57.7°C/W).

Technical Context

The device implements a proprietary Phase-Locked Loop architecture optimized for PCIe 3.0 spectral purity, delivering ≤3 ps RMS jitter (high-frequency band) and ≤60 ps cycle-to-cycle jitter at 100 MHz. Its PLL supports two modulation bandwidths-low-bandwidth (1.75–3 ps) and high-bandwidth (0.45–1 ps)-to meet PCIe 3.0 jitter mask requirements across first harmonic harmonics.

It features dual power domains (VDDA for analog oscillator, VDD for core logic), dedicated IREF pin for external 475 Ω reference resistor enabling precise current-mode HCSL output (IOH = 6×IREF ≈ 2.32 mA), and configurable spread spectrum via single-pin SS1 control with internal pull-up.

Key Specifications

Pinout & Package

Package: 16-pin TQFN (ZH16), 3 mm × 3 mm, 0.5 mm pitch, Pb-free and RoHS-compliant, with exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 3.0 clock generator applications.

Compared with IDT8T49N242BGI and Si53301-A-GM, the PI6C557-01BQZHIEX offers native 3.3 V HCSL drive, hardware spread control, and simpler layout with discrete crystal - making it optimal for cost-sensitive, space-constrained PCIe 3.0 fanout where I²C overhead or dual outputs are unnecessary.

Availability

PI6C557-01BQZHIEX is available at Aetrix Electronics and suitable for PCIe 3.0 server motherboards, industrial embedded computing platforms, and high-density storage appliances requiring stable component supply and EMI-compliant timing.

Supply support for PI6C557-01BQZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated acquired Pericom Semiconductor in 2017 and now manufactures high-performance timing, interface, and signal integrity solutions for datacenter, communications, and industrial markets.

The PI6C557-01BQZHIEX belongs to Pericom's legacy PCIe clock generator product line, designed specifically to meet PCI-SIG Gen3 EMI and jitter requirements in space-constrained, thermally demanding motherboard environments.

FAQ

What is the recommended external crystal specification for PI6C557-01BQZHIEX?

The device requires a 25 MHz fundamental-mode parallel-resonant crystal with load capacitance (CL) of 18 pF and frequency tolerance ≤±30 ppm over -40°C to +85°C. Recommended part numbers include GC2500003 (49S/SMD, 4.0 mm), FY2500107 (5×3.2 mm SMD), and FL2500038 (3.2×2.5 mm SMD). Crystal capacitors must be set to (CL − 8) × 2 = 20 pF effective value.

How is HCSL output termination implemented on the PCB?

HCSL outputs require external 33 Ω series resistors on each CLK line and 49.9 Ω pull-down resistors to ground near the receiver. Routing must follow PCIe Layout Guidelines: non-coupled 50 Ω traces (L1–L3 ≤0.5", ≤0.2", ≤0.2") followed by coupled 100 Ω differential microstrip (L4 = 2–16 inches). The IREF pin must connect to a 475 Ω resistor to set 2.32 mA reference current.

Can PI6C557-01BQZHIEX operate in LVDS mode?

Yes - the device supports LVDS-compatible voltage levels when configured with appropriate external termination: 100 Ω differential load (RP/RQ = 100 Ω) and 150 Ω termination to VDD/2 (RT). Output common-mode voltage shifts to ~1.2 V, and slew rate is adjusted to meet LVDS specifications. No internal register change is needed; only PCB layout and termination differ from HCSL mode.

What is the power-up behavior of spread spectrum control?

SS1 has an internal pull-up resistor, so the device defaults to no-spread mode (SS1 = high) at power-up. To enable -0.5% spread, SS1 must be actively driven low after VDD stabilizes. The spread setting takes effect within 3.0 ms, and tSTABLE (time from VDD ramp to valid output) is 3.0 ms. No external reset sequencing is required beyond standard 3.3 V rail ramp rate (>100 µs).