Diodes Incorporated PI6C557-03BQE

Overview

PI6C557-03BQE from Diodes Incorporated is a PCIe 3.0-compliant spread spectrum clock generator with two HCSL differential outputs, 3.3V supply, 25MHz crystal input, and programmable output frequencies (25/100/125/200MHz) selected via S1:S0 pins. It delivers 0.45ps RMS high-frequency phase jitter and supports -0.5%/-0.75% spread or no spread via SS1:SS0 pins for EMI reduction in PC and embedded host systems.

For engineers reviewing the PI6C557-03BQE datasheet, PI6C557-03BQE pinout, PI6C557-03BQE application, or PI6C557-03BQE equivalent, key selection criteria include PCIe 3.0 jitter compliance, HCSL current-mode drive capability (0.8V differential pair), external spread/frequency configuration logic, and dual-output timing synchronization for multi-lane PCIe root complexes.

Technical Context

The PI6C557-03BQE integrates a proprietary PLL architecture optimized for PCIe 3.0 spectral purity, accepting only a 25MHz fundamental-mode crystal or single-ended clock on X1/CLK and generating two synchronized HCSL output pairs (CLK0/CLK0, CLK1/CLK1) at selectable frequencies. Its internal current reference (IREF pin) sets output drive strength via external 475Ω resistor, yielding 2.32mA reference and 6×IREF = 13.9mA per HCSL source leg.

Spread spectrum modulation is implemented digitally via dedicated SS0/SS1 control pins with fixed 30–33kHz modulation frequency and three discrete spread settings; output enable (OE) provides tri-state control with 10μs enable/disable timing, and all inputs feature internal pull-up resistors for default configuration without external biasing.

Key Specifications

Pinout & Package

PI6C557-03BQE is packaged in a 16-pin QSOP (Q16), 150mil wide, RoHS-compliant and halogen-free "Green" package with exposed thermal pad not present. Pin pitch is 0.025", body width 0.205", and maximum height 0.071".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe 3.0 clock generator applications.

Compared with IDT8T49N242B and Si53320-B-GM, the PI6C557-03BQE uniquely combines dual HCSL outputs, hardware-only configuration, PCIe 3.0-compliant jitter, and spread spectrum in a single 3.3V 16-QSOP package - making it optimal for cost-sensitive, firmware-minimal PCIe timing in industrial and embedded platforms.

Availability

PI6C557-03BQE is available at Aetrix Electronics and suitable for PCIe root complex timing, embedded storage controller clocking, network switch fabric clocking, and medical imaging data acquisition requiring stable component supply and long-term industrial temperature support (-40°C to +85°C).

Supply support for PI6C557-03BQE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors, analog ICs, and timing devices, headquartered in Plano, Texas, with design centers across Asia and manufacturing in IATF 16949-certified facilities.

The PI6C557-03BQE belongs to Diodes' PCIe-optimized clock generator product line, designed specifically to meet stringent Gen3 jitter and EMI requirements in space-constrained PC, server, and industrial embedded applications without firmware dependency.

FAQ

What crystal specifications are required for reliable PI6C557-03BQE operation?

The device requires a 25MHz fundamental-mode parallel-resonant crystal with ≤300ppm frequency tolerance over -40°C to +85°C, 18pF load capacitance, and low ESR (<80Ω). Diodes recommends GC2500003 (49S/SMD, 4.0mm), FY2500081 (5x3.2mm), or FL2500047 (3.2x2.5mm) - all specified at ±20–30ppm and 18pF CL. External load capacitors must be calculated as (CL − 8) × 2 pF.

How is HCSL output termination implemented on the PCB?

Each HCSL output pair (CLK0/CLK0, CLK1/CLK1) requires two external resistors: a 33Ω series resistor (RS) placed close to the PI6C557-03BQE output pin, and a 49.9Ω termination resistor (RT) to ground at the receiver end. This forms a 50Ω single-ended impedance path matching PCIe layout guidelines. The IREF pin must be connected to a 475Ω resistor to set the correct 2.32mA reference current.

Can the PI6C557-03BQE be used with LVDS receivers instead of HCSL?

Yes - the PI6C557-03BQE supports LVDS-compatible voltage levels when configured with appropriate external termination: 100Ω differential termination (RP/RQ = 100Ω each) and 150Ω to ground (RT) per leg. Output common-mode voltage shifts to ~1.2V, meeting LVDS thresholds. However, this requires redesigning the termination network and verifying eye diagram compliance per JEDEC JESD65B.

What is the function of the separate VDDX and GNDX pins?

VDDX and GNDX provide an isolated power/ground domain exclusively for the internal crystal oscillator circuit. Separating this analog-sensitive path from the main VDDA/GNDA digital/analog supply prevents switching noise from the PLL and output drivers from modulating the crystal's resonant frequency - a critical requirement for achieving sub-0.5ps RMS jitter performance in PCIe 3.0 applications.