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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Diodes Incorporated PI6C557-03LE

Name: PI6C557-03LE
Brand: Diodes Incorporated
SKU: PI6C557-03LE
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PI6C557-03LE

Manufacturer:: Diodes Incorporated

Category:: Application Specific Clock/Timing

Package:: 16-TSSOP (0.173", 4.40mm Width)

Datasheet:: PI6C557-03LE.pdf

Description:: IC CLOCK GENERATOR 16TSSOP

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Product details

Overview

PI6C557-03LE from Pericom Semiconductor is a spread spectrum clock generator IC designed for PCI Express and Ethernet clock distribution in PC and embedded systems. It accepts a 25MHz crystal input, delivers two HCSL differential output pairs at 25/100/125/200MHz, supports ±0.25%, −0.5%, −0.75%, or no spread, operates from 3.3V ±10%, and achieves 60ps typical cycle-to-cycle jitter over −40°C to +85°C.

For engineers reviewing the PI6C557-03LE datasheet, PI6C557-03LE pinout, PI6C557-03LE application, or PI6C557-03LE equivalent, key selection considerations include HCSL/LVDS compatibility, spread-spectrum modulation control via SS0/SS1 pins, output frequency selection via S0/S1, OE-driven tri-state capability, and IREF-based current calibration for 50Ω trace impedance matching.

Technical Context

The PI6C557-03LE integrates a proprietary Phase-Locked Loop (PLL) with crystal driver and spread-spectrum modulation circuitry to generate low-jitter differential clocks. Its PLL locks to a 25MHz fundamental-mode parallel-resonant crystal (e.g., GC2500003, CL=18pF), enabling precise synthesis of 25/100/125/200MHz outputs without external dividers or multipliers.

Output configuration is controlled by two 2-bit logic interfaces: S1:S0 selects output frequency, while SS1:SS0 selects spread mode (center-spread ±0.25%, down-spread −0.5% or −0.75%, or no spread). All inputs feature internal pull-up resistors, and OE enables hardware-controlled tri-state of both CLK0 and CLK1 differential pairs.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Frequency	25MHz crystal or single-ended clock - fixed reference for PLL lock and frequency synthesis
Output Frequencies	25/100/125/200MHz - selectable via S1:S0; no external dividers required
Output Type	HCSL differential (0.7V current-mode) - compatible with PCIe Gen1–Gen3 clock receivers
Jitter (Cycle-to-Cycle)	60ps typical - meets PCIe Gen2/Gen3 jitter budget for reliable high-speed link training
Supply Voltage	3.3V ±10% - requires 0.01μF decoupling per VDD pin (VDDX, VDDA)
Spread Spectrum	±0.25%, −0.5%, −0.75%, or none - programmable via SS1:SS0 to reduce EMI peak emissions
Operating Temperature	−40°C to +85°C - qualified for industrial-grade embedded and server motherboard applications

Pinout & Package

Package: 16-pin, 173-mil wide Pb-free Green TSSOP (L package code).

Pin/Terminal	Circuit Role	Design Meaning
1 S0	Frequency select input	LSB of 2-bit output frequency control (00=25MHz, 01=100MHz, 10=125MHz, 11=200MHz)
2 S1	Frequency select input	MSB of 2-bit output frequency control; internal pull-up enables default 200MHz on power-up
3 SS0	Spread select input	LSB of 2-bit spread mode control (00=±0.25%, 01=−0.5%, 10=−0.75%, 11=no spread)
4 X1/CLK	Clock input	Accepts 25MHz crystal or single-ended clock; connects to crystal's first terminal or external oscillator
5 X2	Clock output	Crystal second terminal connection; left unconnected when using external clock source
6 OE	Output enable	Active-low tri-state control for both CLK0 and CLK1 differential pairs; internal pull-up defaults to enabled
7 GNDX	Crystal ground	Dedicated analog ground for crystal circuit; must be connected to system ground plane
8 SS1	Spread select input	MSB of 2-bit spread mode control; determines center-spread vs. down-spread behavior
9 IREF	Current reference output	Drives external 475Ω resistor to set 2.32mA reference; scales HCSL output current (IOH = 6×IREF)
10 CLK1	Differential output	True leg of second HCSL pair; requires series termination (RS=33Ω) and 49.9Ω to ground per PCIe layout guidelines
11 CLK1	Differential output	Complement leg of second HCSL pair; routed as tightly coupled 100Ω differential pair (L4 = 2–16 inch)
12 VDDA	Analog supply	+3.3V supply for PLL, crystal driver, and analog circuitry; requires local 0.01μF decoupling
13 GNDA	Analog ground	Reference ground for analog blocks; separate from digital ground but tied at single point
14 CLK0	Differential output	True leg of first HCSL pair; identical routing requirements as CLK1
15 CLK0	Differential output	Complement leg of first HCSL pair; matched length and coupling critical for skew <50ps
16 VDDX	Clock supply	+3.3V supply for crystal oscillator circuit; independent decoupling required

Key Features

Feature	Design Value
Programmable Spread Spectrum	Four discrete spread modes (±0.25%, −0.5%, −0.75%, none) reduce EMI peaks by up to 15dB without altering system timing margins
HCSL Output Compliance	0.7V current-mode differential drive meets PCIe Gen1–Gen3 electrical specifications with 50Ω trace impedance and defined rise/fall times (175–700ps)
LVDS-Compatible Mode	Configurable output voltage levels (1.0–1.3V swing) support legacy LVDS receivers without external level shifters
Low-Jitter PLL Architecture	60ps typical cycle-to-cycle jitter ensures robust PCIe link training and stable SerDes operation across temperature and voltage
Hardware-Controlled Tri-State	OE pin enables synchronous shutdown of both differential clock outputs during hot-plug or power-state transitions

Applications

PCI Express Root Complex Clocking

Ethernet PHY Reference Clocking

Use Scenario: Providing primary reference clock to CPU PCIe root complex and multiple downstream slots on a server motherboard.

IC Role / Device Role / Timing Role: Primary spread-spectrum clock generator delivering two synchronized 100MHz HCSL differential outputs to meet PCIe Gen2 timing and EMI requirements.

Use Value: Enables simultaneous clocking of multiple PCIe lanes while reducing radiated emissions below FCC Class B limits without compromising link stability.

Use Scenario: Supplying 125MHz reference clock to 10GBASE-T Ethernet PHYs in enterprise switches.

IC Role / Device Role / Timing Role: Low-jitter clock source configured for −0.5% down-spread to suppress narrowband EMI at 125MHz fundamental and harmonics.

Use Value: Meets IEEE 802.3an EMI compliance for 10GBase-T while maintaining <100ps cycle-to-cycle jitter for SERDES CDR lock.

Embedded Industrial Controller Timing

Multi-Function Peripheral Clock Hub

Use Scenario: Generating synchronized clocks for FPGA fabric, DDR3 memory controller, and PCIe endpoint in an industrial PLC.

IC Role / Device Role / Timing Role: Single-chip clock hub providing 25MHz (FPGA logic), 100MHz (PCIe), and 200MHz (DDR3 PHY) from one 25MHz crystal.

Use Value: Eliminates need for multiple oscillators or clock buffers, reducing BOM count and board area while ensuring deterministic inter-clock phase alignment.

Use Scenario: Driving clock inputs for USB 3.0 controller, SATA controller, and audio codec on a compact laptop motherboard.

IC Role / Device Role / Timing Role: Multi-output clock generator configured for no-spread 25MHz (USB), 100MHz (SATA), and 125MHz (audio) with independent OE control.

Use Value: Allows dynamic clock gating per subsystem to reduce platform idle power without affecting active peripherals' timing integrity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar spread-spectrum clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT8T49N242A	Supports 1–2100MHz output range; integrated EEPROM for custom spread profiles; higher pin count (32-QFN)	Targeted at high-end telecom and datacom where programmable modulation depth/frequency is required	Choose when field-upgradable spread parameters or wider frequency coverage outweigh cost and footprint constraints
ICS843002AGI	Two LVDS outputs only; no HCSL mode; fixed −0.25% spread; lower jitter (45ps typ); 24-TSSOP	Suitable for legacy LVDS-only systems requiring minimal EMI reduction and highest jitter performance	Choose when HCSL compatibility is unnecessary and sub-50ps jitter is mandatory for ultra-high-speed SerDes

Compared with IDT8T49N242A and ICS843002AGI, the PI6C557-03LE offers optimal balance of PCIe-specific HCSL drive strength, four discrete spread modes, compact 16-TSSOP footprint, and industrial temperature support-making it ideal for cost-sensitive, space-constrained PC and embedded PCIe designs.

Availability

PI6C557-03LE is available at Aetrix Electronics and suitable for PCIe root complex clocking, Ethernet PHY reference timing, embedded industrial controller synchronization, and multi-peripheral clock hub applications requiring stable component supply across production lifecycles.

Supply support for PI6C557-03LE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) specialized in high-performance timing, interface, and signal-integrity solutions for computing, communications, and consumer electronics before its 2016 acquisition.

The PI6C557-03LE belongs to Pericom's PCI Express clock generator product line, engineered specifically to meet PCIe Gen1–Gen3 EMI and jitter specifications while simplifying board-level clock tree design through integrated spread-spectrum control and dual-HCSL outputs.

FAQ

What crystal specifications are required for stable operation of the PI6C557-03LE?

The PI6C557-03LE requires a 25MHz fundamental-mode parallel-resonant crystal with load capacitance of 18pF and frequency tolerance ≤±30ppm across −40°C to +85°C. Recommended parts include GC2500003 (49S/SMD, 4.0mm), FY2500081 (5x3.2mm), and FL2500047 (3.2x2.5mm). External load capacitors must be calculated as (CL − 8) × 2 pF.

How is HCSL output current calibrated using the IREF pin?

The IREF pin sources a precision current that sets the HCSL output drive strength. A 475Ω resistor connected between IREF and ground establishes a 2.32mA reference current, resulting in 6×IREF = 13.9mA output current per HCSL leg. This matches standard 50Ω PCB trace impedance and ensures proper voltage swing (660–850mV) under 50Ω termination.

Can the PI6C557-03LE be used with LVDS receivers, and what layout changes are needed?

Yes-the PI6C557-03LE supports LVDS-compatible voltage levels (1.0–1.3V swing) by adjusting external termination. For LVDS, replace the PCIe-specified 33Ω series and 49.9Ω ground resistors with 100Ω differential termination (RP=RQ=100Ω) and 150Ω common-mode bias (RT=150Ω), per the device's LVDS Layout Guidelines section.

What is the maximum allowable skew between CLK0 and CLK1 differential pairs?

The PI6C557-03LE guarantees ≤50ps output skew between CLK0 and CLK1 differential pairs when measured at VDD/2 crossing point under recommended operating conditions (VDD = 3.3V ±10%, TA = −40°C to +85°C). Maintaining matched trace lengths (<50ps delay difference) and identical routing topology is essential to preserve this specification in layout.

PI6C557-03LE Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: -

Package/Case:: 16-TSSOP (0.173", 4.40mm Width)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, PCI Express (PCIe)

Input:: CMOS, Crystal

Output:: HCSL, LVDS

Number of Circuits:: 1

Ratio - Input:Output:: 1:2

Differential - Input:Output:: No/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 16-TSSOP

PI6C557-03LE FAQ

1.How can I place an order for PI6C557-03LE through Aetrix?

Please submit a Request for Quotation (RFQ) for PI6C557-03LE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PI6C557-03LE reliable?

The price and inventory of PI6C557-03LE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PI6C557-03LE is usually 5 days.

3.What payment methods are accepted for PI6C557-03LE?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PI6C557-03LE transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PI6C557-03LE?

PI6C557-03LE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PI6C557-03LE order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PI6C557-03LE?

For technical support, including PI6C557-03LE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PI6C557-03LE requirements.

6.How does Aetrix verify that PI6C557-03LE is sourced from the original manufacturer or authorized distributors?

All PI6C557-03LE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PI6C557-03LE meets industry standards.

7.What is the process for return or replacement of PI6C557-03LE?

All PI6C557-03LE units undergo pre-shipment inspection (PSI). If there is an issue with PI6C557-03LE, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PI6C557-03LE part is unused and in its original packaging.

Return procedure for PI6C557-03LE:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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