Diodes Incorporated PI6C557-05QLE

Overview

PI6C557-05QLE from Pericom is a PCIe® 2.0-compliant spread spectrum clock generator with AEC-Q100 qualification for automotive applications. It accepts a 25 MHz crystal input and delivers four differential HCSL output pairs at selectable 100 MHz or 200 MHz frequencies, with RMS phase jitter of 2.1 ps (typ), cycle-to-cycle jitter of 40 ps (typ), and spread options of –0.5%, –1.0%, –1.5%, or no spread.

For engineers reviewing the PI6C557-05QLE datasheet, PI6C557-05QLE pinout, PI6C557-05QLE application, or PI6C557-05QLE equivalent, key selection criteria include PCIe Gen 2 timing compliance, HCSL/LVDS dual-mode output configuration, spread-spectrum control via S[2:0] pins, and automotive-grade thermal and reliability specs across –40°C to +85°C ambient.

Technical Context

The device uses a proprietary PLL architecture to synthesize 100/200 MHz differential clocks from a 25 MHz fundamental-mode crystal, supporting both HCSL (0.7 V current-mode) and LVDS-compatible voltage-mode outputs. Spread spectrum modulation is digitally controlled via three external pins (S2–S0), enabling eight discrete configurations including no-spread mode.

It features separate analog (VDDODA/GNDODA) and digital (VDDXD/GNDXD) power domains, precision IREF current reference (2.32 mA typical with 475 Ω resistor), and tri-state output enable (OE) with 10 µs enable/disable timing. All outputs are open-source drivers requiring external termination per PCIe layout guidelines.

Key Specifications

Pinout & Package

Package: Pb-free and Green 20-pin, 173-mil wide TSSOP (JEDEC MO-153).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar spread spectrum clock generator applications.

Compared with ICS9FGP102B and Si53301-A01AGM, the PI6C557-05QLE provides deterministic, pin-strapped spread-spectrum control and PCIe Gen 2–compliant jitter without software overhead-ideal for automotive and industrial systems where reliability, EMI control, and zero-firmware clocking are critical.

Availability

PI6C557-05QLE is available at Aetrix Electronics and suitable for automotive infotainment systems, PCIe-based ADAS ECUs, and industrial embedded vision systems requiring stable component supply with AEC-Q100 assurance and long-term lifecycle support.

Supply support for PI6C557-05QLE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (acquired by Diodes Incorporated in 2016) specialized in high-performance timing, interface, and signal-integrity solutions for computing, communications, and automotive markets.

The PI6C557-05QLE belongs to Pericom's PCIe clock generator product line, engineered specifically to meet stringent EMI reduction and timing accuracy requirements in automotive and industrial PCIe 2.0 applications.

FAQ

What crystal specifications are required for stable operation?

The PI6C557-05QLE requires a 25 MHz fundamental-mode parallel-resonant crystal with ±15 ppm frequency tolerance, 20 pF load capacitance, and stability ≤±20 ppm over –40°C to +85°C. Pericom recommends FL2500184Q (3.2×2.5 mm, SMD) or equivalent. External load capacitors C1/C2 = 27 pF are suggested for CL = 20 pF crystals.

How is HCSL output current set, and what resistor value is needed?

HCSL output current is set by the IREF pin, which sinks a precision current (IREF = VREF / RR). With a 475 Ω resistor to ground, IREF = 2.32 mA (typ), yielding IOH = 6 × IREF = 13.9 mA per output leg. This matches standard HCSL 50 Ω single-ended drive strength and enables proper 100 Ω differential termination.

Can the device operate in LVDS mode, and what layout changes are needed?

Yes-the PI6C557-05QLE supports LVDS-compatible voltage levels by changing external termination: replace HCSL's 33 Ω series + 49.9 Ω ground resistors with LVDS's 100 Ω differential termination (RP/RQ = 100 Ω, RT = 150 Ω). Layout must follow LVDS routing rules: non-coupled 50 Ω traces for L1/L2, then coupled 100 Ω differential for L3.

What is the power-down current consumption, and how is PD pin used?

When PD (Pin 7) is driven low, the device enters power-down mode with IDD < 100 µA (typ), disabling internal PLL and oscillator while retaining pin states. The internal pull-up resistor keeps PD high by default; no external pull-up is required. Power-down recovery time is 3.0 ms after VDD stabilizes at 3.3 V.