Diodes Incorporated PI6C5913004ZHIEX

Overview

PI6C5913004ZHIEX from Diodes Incorporated is a 3 GHz, 1:4 LVPECL fanout buffer with pin-selectable dual differential inputs (REF_IN0/REF_IN1), four differential LVPECL output pairs (Q0–Q3), and integrated VREF_AC bias generator for AC-coupled input interfaces. It supports LVPECL, LVDS, CML, and LVCMOS input levels and delivers <20 ps output-to-output skew in a 16-pin TQFN package - ideal for high-speed clock distribution in PCIe Gen3/Gen4 reference clock trees.

For engineers reviewing the PI6C5913004ZHIEX datasheet, PI6C5913004ZHIEX pinout, PI6C5913004ZHIEX application, or PI6C5913004ZHIEX equivalent, key selection criteria include additive jitter (<20 fs RMS), dual-input flexibility, VREF_AC output for AC-coupled signal recovery, and compatibility with 2.5V/3.3V supplies across -40°C to +85°C industrial temperature range.

Technical Context

The PI6C5913004 implements a low-skew, current-mode logic (CML)-based fanout architecture with internal termination and bias generation. Its REF_SEL pin selects between two independent differential input channels, each supporting AC- or DC-coupled operation via VREF_AC output (biased at VDD−1.4 V).

All four LVPECL output pairs share matched propagation delay paths and are internally terminated to minimize reflections and skew. The device uses separate power (VDD) and ground (GND) pins plus an exposed thermal pad (ePad) connected to GND, enabling stable 3 GHz operation under 150 mA typical supply current.

Key Specifications

Pinout & Package

Package: 16-pin TQFN (W-QFN3030-16), 3 mm × 3 mm, 0.5 mm pitch, exposed thermal pad (ePad) requiring GND connection for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVPECL fanout buffer applications.

Compared with IDT8T49N242A, PI6C5913004ZHIEX offers lower power and simpler layout but no jitter attenuation; compared with NB3N551, it delivers double the outputs, dual-input selection, and integrated VREF_AC - making it optimal for scalable, multi-source clock trees in space-constrained designs.

Availability

PI6C5913004ZHIEX is available at Aetrix Electronics and suitable for PCIe Gen4 reference clock distribution, 10GbE synchronous Ethernet timing, and SAS/SATA multi-channel storage controllers requiring stable component supply, consistent lead times, and long-term lifecycle support.

Supply support for PI6C5913004ZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal ICs for power management, signal integrity, and connectivity applications.

The PI6C5913004 belongs to Diodes' high-speed clock buffer product line, engineered specifically for low-jitter, multi-output clock distribution in datacenter, telecom, and industrial infrastructure systems.

FAQ

What input standards does the PI6C5913004ZHIEX support?

The PI6C5913004ZHIEX accepts LVPECL, LVDS, CML, SSTL, and LVCMOS input levels across both differential input pairs. Input voltage swing ranges from 0.2 V to 1.7 V, and DC or AC coupling is supported using the internal VREF_AC output for biasing. No external level shifters or terminations are required for standard compliance.

How is VREF_AC used in AC-coupled input configurations?

VREF_AC provides a stable DC bias at VDD−1.4 V, which is connected to the AC-coupling capacitor's receiver-side node to restore the common-mode voltage for LVDS, CML, or HCSL inputs. This eliminates the need for external resistor dividers and ensures correct input threshold alignment across temperature and voltage variations.

Can PI6C5913004ZHIEX drive HCSL loads directly?

No - the PI6C5913004ZHIEX outputs LVPECL, not HCSL. However, its LVPECL outputs can drive HCSL inputs using an external Thevenin termination (e.g., 450 Ω pull-up + 60 Ω pull-down) to generate ~0.4 V common-mode voltage. This configuration is validated in Diodes' application notes for PCIe reference clock interfacing.

What is the recommended power supply decoupling for this device?

Each VDD pin requires a minimum 0.1 µF ceramic capacitor placed adjacent to the pin on the component side of the PCB. For improved high-frequency noise suppression, add a 1 µF bulk capacitor within 10 mm. The exposed thermal pad (ePad) must be soldered to a solid GND plane to ensure thermal stability and low-impedance return path.