Diodes Incorporated PI6C5946002ZHIEX

Overview

PI6C5946002ZHIEX from Pericom Semiconductor is a high-performance 1-to-2 CML clock/data fanout buffer with internal termination, designed for ultra-high-speed signal distribution in serial link timing paths. It supports up to 6 GHz input clock frequency and 12 Gbps data rate, delivers <20 ps output-to-output skew, and operates from 3.3 V ±10% or 2.5 V ±5% supply across –40°C to +85°C - used in PCIe Gen3/4 reference clock distribution and XAUI/SATA/Fibre Channel interconnects.

For engineers reviewing the PI6C5946002ZHIEX datasheet, PI6C5946002ZHIEX pinout, PI6C5946002ZHIEX application, or PI6C5946002ZHIEX equivalent, key selection criteria include differential input compatibility (CML/LVDS/SSTL), additive jitter ≤40 fs RMS (156.25 MHz, 12 kHz–20 MHz), dual CML output pair drive capability, and TQFN-16 package thermal performance (θ_JA = 54.4°C/W).

Technical Context

The PI6C5946002 implements a fully differential, current-mode logic (CML) fanout architecture with on-die 100 Ω differential input termination and configurable AC/DC coupling support via REF_IN± and VREF-AC pins. Its synchronous enable (EN) pin controls both output pairs simultaneously with internal 25 kΩ pull-up.

It accepts wide-swing inputs (0.2–1.7 V differential) and delivers rail-to-rail CML outputs (325–400 mV single-ended swing), with propagation delay of 400 ps and duty cycle stability of 48–52% at 1 GHz. Output skew is specified under matched load and supply conditions, not system-level routing.

Key Specifications

Pinout & Package

PI6C5946002ZHIEX is housed in a Pb-free, green 16-pin Thin Quad Flat No-Lead (TQFN) package (code ZH), 3 mm × 3 mm × 0.8 mm, with exposed thermal pad for enhanced heat dissipation (θ_JC = 40.8°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed clock/data fanout buffer applications.

Compared with ICS85411AMLF and SY89851UMG, the PI6C5946002ZHIEX uniquely combines internal CML/LVDS/SSTL termination, VREF-AC bias generation, and sub-20 ps skew in a 3×3 mm TQFN - delivering lowest system-level component count and highest timing fidelity for next-gen serial interconnects.

Availability

PI6C5946002ZHIEX is available at Aetrix Electronics and suitable for PCIe Gen4 reference clock distribution, SATA III timing, XAUI fanout, and Fibre Channel 10G applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for PI6C5946002ZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Pericom Semiconductor (now part of Diodes Incorporated) is a fabless semiconductor company specializing in high-speed timing, signal integrity, and interface solutions for datacom, telecom, and computing markets.

The PI6C5946002 belongs to Pericom's high-frequency clock buffer product line, engineered specifically for low-jitter, low-skew distribution of serial link reference clocks and data streams in PCIe, SATA, Fibre Channel, and XAUI systems.

FAQ

What input standards does the PI6C5946002ZHIEX support?

The PI6C5946002ZHIEX supports CML, LVDS, and SSTL input levels with internal 100 Ω differential termination. It accepts both AC- and DC-coupled inputs via REF_IN± and uses VREF-AC to bias AC-coupled configurations. Input voltage swing ranges from 0.2 V to 1.7 V differential, and VIH/VIL thresholds are defined for LVCMOS/LVTTL control pins like EN.

How is output skew measured and what conditions affect it?

Output-to-output skew is measured at the differential crossing point between Q0 and Q1 outputs under matched load (100 Ω differential), equal supply voltage, and ambient temperature (–40°C to +85°C). It excludes PCB routing skew and is specified as <20 ps maximum. Skew increases with mismatched termination, unequal trace lengths, or supply noise - hence the datasheet specifies test conditions explicitly.

Can the PI6C5946002ZHIEX drive HCSL loads directly?

No - the PI6C5946002ZHIEX outputs CML signals (325–400 mV single-ended swing, ~400 mV differential), while HCSL requires ~0.4 V common-mode and 800 mV differential swing. However, its CML outputs can drive HCSL inputs using an external 450 Ω/60 Ω Thevenin termination to synthesize the correct V_cm, as documented in Figure 11 of the datasheet.

What is the role of the VREF-AC pin and how should it be used?

VREF-AC is an output pin biased at VDD − 1.4 V, used to set the common-mode voltage for AC-coupled inputs. When REF_IN± are AC-coupled, VTH must be tied to VREF-AC to establish correct input bias. VREF-AC is not intended as a power rail - it sources limited current and must not be loaded with capacitors >100 pF or resistors <10 kΩ.