Diodes Incorporated PI6C5946004ZHIEX

Overview

PI6C5946004ZHIEX from Diodes Incorporated is a high-performance 1-to-4 CML clock/data fanout buffer with internal termination, supporting up to 6 GHz input clock frequency and 12 Gbps data rate. It features four differential CML output pairs, <20 ps output-to-output skew, and dual supply compatibility (3.3 V ±10% or 2.5 V ±5%). It is used in high-speed serial interconnects including PCIe Gen3/4, SATA, Fiber Channel, and XAUI.

For engineers reviewing the PI6C5946004ZHIEX datasheet, PI6C5946004ZHIEX pinout, PI6C5946004ZHIEX application, or PI6C5946004ZHIEX equivalent, key selection criteria include additive jitter (<0.05 ps max), input level flexibility (CML/LVDS/SSTL), AC/DC coupling support via VREF-AC and VTH, and thermal performance (ΘJA = 54.4 °C/W) in high-density PCB layouts.

Technical Context

This device implements a fully differential, low-skew fanout architecture with on-chip 100 Ω differential input termination and programmable synchronous enable (EN). Its CML outputs drive 100 Ω differential loads with 325–400 mV single-ended swing and maintain <400 ps propagation delay across temperature and voltage.

The input stage accepts AC- or DC-coupled signals via REF_IN+/REF_IN−, with VTH tied to VREF-AC (VDD −1.4 V) for AC-coupled biasing. Internal 25 kΩ pull-up on EN enables default-active operation without external logic, and unused inputs may be left floating or grounded via 1 kΩ for reliability.

Key Specifications

Pinout & Package

PI6C5946004ZHIEX is housed in a 16-pin TQFN package (ZH footprint, 3 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad for enhanced heat dissipation. Pin 13 is GND; pins 7 and 14 are VDD; EN (pin 8) has internal 25 kΩ pull-up; VREF-AC (pin 10) provides bias for AC-coupled inputs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock/data fanout applications.

Compared with IDT8T49N242B and NB3N551, PI6C5946004ZHIEX uniquely combines CML/LVDS/SSTL input flexibility, internal termination, 12 Gbps capability, and sub-0.05 ps jitter-making it the only choice for compact, high-density PCIe Gen4 and SATA Gen3 fanout without external biasing or level-shifting.

Availability

PI6C5946004ZHIEX is available at Aetrix Electronics and suitable for PCIe Gen4 reference clock distribution, SATA Gen3 data fanout, and Fiber Channel 16G timing applications requiring stable component supply, RoHS-compliant packaging, and lead-free manufacturing traceability.

Supply support for PI6C5946004ZHIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-performance timing, signal integrity, and power management solutions for industrial, computing, and communications markets.

The PI6C family targets high-speed clock and data distribution in serial interconnect systems, with PI6C5946004 engineered specifically for ultra-low skew and jitter in PCIe, SATA, and Fibre Channel infrastructure.

FAQ

Can PI6C5946004ZHIEX accept LVPECL inputs directly?

No. The device does not support direct LVPECL input due to incompatible common-mode voltage range. LVPECL signals must be AC-coupled through 50 Ω series resistors with VREF-AC used as the bias reference, as shown in Figure 3 of DS41566. DC-coupled LVPECL will exceed absolute maximum input voltage ratings and risk damage.

What is the recommended decoupling for VDD pins?

Each VDD pin (pins 7 and 14) requires a minimum 0.1 µF ceramic capacitor placed adjacent to the pin on the component side of the PCB. For improved high-frequency noise suppression, add a 1 µF capacitor in parallel. Avoid shared vias between decoupling caps and GND; connect each cap directly to pin 13 (GND) or the exposed thermal pad.

Is the EN pin compatible with 1.8 V logic control?

Yes. With VDD = 3.3 V, VIH(min) = 1.2 V and VIL(max) = 0.4 × VIH − 0.1 V ≈ 0.38 V, so a 1.8 V CMOS driver meets both thresholds. With VDD = 2.5 V, VIH(min) = 2.0 V, making 1.8 V insufficient - in that case, a level shifter or 2.5 V-compatible GPIO is required.

How should unused CML outputs be handled?

Unused CML outputs (e.g., Q2+/Q2− if only three channels are needed) must be left open - not terminated or shorted. Connecting them to any load increases IDD by ~25 mA per pair and raises die temperature without benefit. The datasheet explicitly recommends leaving outputs unconnected to minimize power and thermal stress.