Diodes Incorporated PI6CB18200ZDIEX

Overview

PI6CB18200ZDIEX from Diodes Incorporated is a 2-output, very low power PCIe Gen1–Gen4 clock buffer with HCSL input and dual differential low-power HCSL outputs. It operates at 1.8V supply, supports 100MHz (default), 50MHz, or 125MHz via SMBus configuration, and delivers <50ps differential cycle-to-cycle jitter and <50ps output-to-output skew - meeting stringent PCIe timing requirements in server, storage, and high-speed computing applications.

For engineers reviewing the PI6CB18200ZDIEX datasheet, PI6CB18200ZDIEX pinout, PI6CB18200ZDIEX application, or PI6CB18200ZDIEX equivalent, key selection criteria include PCIe Gen4-compliant jitter performance, individual output enable control (OE0#/OE1#), programmable slew rate/amplitude per output, PLL bypass mode, and 3.3V-tolerant SMBus interface for flexible board-level configuration.

Technical Context

This device implements a proprietary analog PLL architecture optimized for ultra-low additive phase jitter (<0.05ps RMS for PCIe Gen4) and fast lock time (20ms). Its dual-output structure isolates Q0 and Q1 paths with independent enable pins and configurable bandwidth (low/high PLL BW or bypass), enabling precise skew management across multi-lane PCIe root complexes and switches.

The clock buffer accepts a differential HCSL reference (VIHDIF = 600–1150mV, VILDIF = –300–300mV) and generates two matched low-power HCSL outputs (VOH = 660–900mV, VOL = –150–150mV) with programmable amplitude (0.6–0.9V) and slew rate (0.4–6V/ns), all while maintaining <1.0ps integrated phase jitter in Gen3/Gen4 CDR bands.

Key Specifications

Pinout & Package

Package: 24-lead 4×4mm TQFN (ZD code), lead-free and halogen-free "Green" construction per RoHS 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53302-D02, the PI6CB18200ZDIEX uniquely combines per-output enable, SMBus-programmable frequency/slew/amplitude, and PLL-bypass mode - enabling unified clocking across PCIe Gen4, Ethernet, and FPGA platforms within a single 4×4mm footprint.

Availability

PI6CB18200ZDIEX is available at Aetrix Electronics and suitable for PCIe Gen4 server motherboards, NVMe storage controllers, OCP network interface cards, and FPGA-based acceleration platforms requiring stable component supply and full RoHS 3 compliance.

Supply support for PI6CB18200ZDIEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for industrial, computing, and communications markets.

The PI6CB18200 belongs to Diodes' PCIe-optimized clock buffer product line, designed specifically to meet Gen1–Gen4 jitter, skew, and power requirements in space-constrained, thermally demanding server and storage applications.

FAQ

What is the minimum input swing required for reliable lock at 100MHz?

The PI6CB18200ZDIEX requires a differential input swing of at least 300mVpp (VIHDIF − VILDIF) for guaranteed PLL lock at 100MHz. The specified input common-mode range is 150–1000mV, and typical HCSL input thresholds are met with standard 33Ω-terminated sources. Input leakage is ±5µA, ensuring robust operation with typical PCIe clock drivers.

Can OE0# and OE1# be used simultaneously to implement staggered output enable timing?

Yes - OE0# and OE1# operate independently with no internal coupling. Each has an internal pull-down and responds within 1–3 clock cycles of assertion/deassertion. This allows precise sequencing, such as enabling Q0 for CPU PCIe lanes before Q1 for peripheral slots, reducing inrush current and improving system-level power ramp control.

Does the SMBus interface retain configuration after power cycling?

No - SMBus registers (e.g., frequency, amplitude, slew) are volatile and reset to default values (100MHz, 0.7V, slow slew) on power-up. Configuration must be reloaded by the host processor or BMC at boot. Strapping pins (BW_SEL_TRI) provide non-volatile mode selection (PLL bypass, low/high BW) without firmware intervention.

How does PLL bypass mode affect jitter performance compared to locked PLL mode?

In PLL bypass mode, the device routes the input clock directly to outputs with propagation delay of 2800–4500ps and cycle-to-cycle jitter of 125ps (vs. 14–50ps in PLL mode). This mode trades jitter performance for deterministic latency and immunity to PLL-induced peaking - ideal for applications using ultra-low-jitter crystal sources where added PLL noise is undesirable.