Diodes Incorporated PI6CB18401ZHIEX

Overview

PI6CB18401 from Diodes Incorporated is a 4-output, very low power PCIe Gen1–Gen4 clock buffer with integrated HCSL output termination, 1.8V supply, and configurable PLL-based jitter suppression. It accepts a differential HCSL input (100/50/125 MHz) and delivers four low-skew, individually enabled HCSL outputs compliant with PCIe timing specifications. Used in high-speed server motherboard clock distribution.

For engineers reviewing the PI6CB18401 datasheet, PI6CB18401 pinout, PI6CB18401 application, or PI6CB18401 equivalent, key selection criteria include differential cycle-to-cycle jitter (<50 ps), on-chip 85Ω HCSL termination per output, SMBus- or strapping-configurable slew rate/amplitude, and support for PCIe Gen4-compliant phase jitter (≤0.5 ps RMS).

Technical Context

The PI6CB18401 implements a proprietary analog PLL architecture with selectable loop bandwidth (1–4 MHz) to suppress input jitter while maintaining PCIe Gen4 phase noise requirements. Its PLL can be bypassed for direct fanout mode, enabling deterministic propagation delay (3–4.5 ns) and eliminating lock time overhead.

It supports dual configuration interfaces: tri-state strapping pins (BW_SEL_TRI, SADR_TRI) for static setup and a 3.3V-tolerant SMBus interface (400 kHz max) for dynamic reconfiguration of output amplitude (0.6–0.9 V), slew rate (0.4–6.5 V/ns), and input frequency (100/50/125 MHz).

Key Specifications

Pinout & Package

Package: 32-lead, 5×5 mm TQFN (0.5 mm pitch), thermally enhanced with exposed pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242 and Si53302, the PI6CB18401 uniquely combines 1.8 V operation, on-chip HCSL termination, SMBus configurability, and PCIe Gen4-compliant jitter in a single low-power package-making it optimal for space-constrained, thermally sensitive server and AI hardware.

Availability

PI6CB18401 is available at Aetrix Electronics and suitable for PCIe Gen4 server motherboards, multi-slot NVMe storage enclosures, 5G Ethernet switch fabrics, and AI accelerator board clock trees requiring stable component supply and long-term lifecycle support.

Supply support for PI6CB18401 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-performance analog, logic, and timing solutions for computing, communications, and industrial markets.

The PI6CB18401 belongs to Diodes' PCIe clock buffer product line, engineered specifically for low-power, high-density server and data center applications demanding Gen4 timing compliance and simplified layout through integrated termination.

FAQ

What is the minimum startup time after PD# de-assertion?

The PI6CB18401 requires 20 ms for PLL lock and 10 ms for full output stabilization after PD# de-assertion, totaling 30 ms before outputs meet PCIe Gen4 jitter and skew specifications. This includes internal power rail ramp-up, PLL acquisition, and output driver settling.

Can the device operate with a 50 MHz input without SMBus configuration?

No. The default strapping state configures the device for 100 MHz operation. To use 50 MHz, the Frequency Select Register (Byte 3) must be written via SMBus to set FSEL[1:0] = 01; strapping-only configuration does not support non-default frequencies.

How does on-chip termination affect PCB layout compared to external resistors?

On-chip 85 Ω termination eliminates eight 0402 resistors per output pair (16 total), removing 16 solder joints, associated parasitic inductance, and routing congestion near the IC. This simplifies layer stackup, improves signal integrity margin, and reduces manufacturing defect risk in high-density server PCBs.

Is the SMBus interface functional during PLL lock acquisition?

Yes. The SMBus interface remains fully operational during PLL lock acquisition and after power-up. Configuration registers can be written at any time-even while the PLL is locking-enabling dynamic parameter adjustment without interrupting clock output stability.