Diodes Incorporated PI6CB184Q2ZHQEX

Overview

PI6CB184Q2ZHQEX from Diodes Incorporated is a 4-output, automotive-grade PCIe Gen 4 clock buffer with integrated PLL, HCSL input (100/50/125 MHz), four differential low-power HCSL outputs with on-chip 50 Ω termination per pair, and AEC-Q100 Grade 2 qualification (–40°C to +105°C). It delivers <50 ps differential cycle-to-cycle jitter and <50 ps output-to-output skew for high-speed serial link timing in ADAS domain controllers.

For engineers reviewing the PI6CB184Q2ZHQEX datasheet, PI6CB184Q2ZHQEX pinout, PI6CB184Q2ZHQEX application, or PI6CB184Q2ZHQEX equivalent, key selection criteria include PCIe Gen 4 compliance, individual output enable control (OE0#–OE3#), SMBus-configurable slew rate/amplitude per output, 1.8 V core supply, and tri-level strapping for PLL bandwidth mode selection.

Technical Context

The PI6CB184Q2ZHQEX implements a proprietary low-jitter PLL architecture with selectable loop bandwidth (low/high/bypass) via BW_SEL_TRI, enabling optimized phase noise performance across PCIe Gen 1–4 and Ethernet 50/125 MHz use cases. Its input stage accepts HCSL differential signals with 300–1450 mVpp swing and supports single-ended biasing.

All four HCSL outputs feature independent enable/disable control, programmable amplitude (0.6–0.9 V), and dual-slew-rate settings (slow/fast), with differential outputs held inactive until PLL lock detection. The device uses separate analog (VDDA/GNDA), digital (VDD_DIG/GND_DIG), and output (VDDO/GND) power domains to isolate noise coupling.

Key Specifications

Pinout & Package

Package: 32-contact TQFN 5×5 mm (SWP) with sidewall plating - thermally enhanced, automotive-qualified footprint with exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with Si53320-A01AGM and ICS843002AGI-01LFT, the PI6CB184Q2ZHQEX uniquely combines AEC-Q100 Grade 2 qualification, on-chip HCSL termination, SMBus-programmable amplitude/slew per output, and multi-frequency support - making it the only drop-in solution for next-gen automotive PCIe Gen 4 + Ethernet coexistence systems.

Availability

PI6CB184Q2ZHQEX is available at Aetrix Electronics and suitable for ADAS domain controllers, automotive Ethernet gateways, infotainment head units, and telematics control units requiring stable component supply across extended temperature ranges and long automotive program lifecycles.

Supply support for PI6CB184Q2ZHQEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and integrated circuits, specializing in high-reliability solutions for automotive, industrial, and computing markets with IATF 16949-certified manufacturing.

The PI6CB184Q2ZHQEX belongs to Diodes' automotive clock buffer product line, engineered specifically for PCIe Gen 4 and multi-protocol Ethernet timing in safety-critical vehicle systems - emphasizing low jitter, AEC-Q100 compliance, and robust configuration flexibility.

FAQ

What is the minimum startup time from power-on to stable 100 MHz outputs?

The PI6CB184Q2ZHQEX achieves full output stability within 10 ms after VDD reaches regulation and PD# is de-asserted, including 20 ms PLL lock time and 1 ms clock stabilization. This meets automotive fast-boot requirements for driver information systems that must initialize within 100 ms of ignition-on.

Can the device operate with a 50 MHz input and generate 50 MHz outputs without PLL involvement?

Yes - the PI6CB184Q2ZHQEX supports PLL bypass mode via BW_SEL_TRI = M (middle voltage), allowing direct fanout of 50 MHz input to all four outputs with propagation delay of 3.0–4.5 ns (Grade 2). This mode eliminates PLL-induced jitter and is validated for 100BASE-T1 Ethernet PHY clocking.

How does the on-chip 50 Ω termination affect PCB layout compared to discrete termination?

The integrated 50 Ω source termination eliminates eight 50 Ω resistors (two per HCSL pair), reducing PCB area by ~12 mm² and removing stubs that cause reflections. Layout requires only controlled 100 Ω differential traces from Qx+/Qx− to receivers - no series resistors or parallel AC-coupling caps needed at the buffer side.

Is SMBus communication possible while the device is in power-down mode?

No - SMBus functionality is disabled when PD# is asserted low. Configuration registers retain their last-written values during power-down, but SCLK/SDATA pins are high-impedance and cannot be accessed until PD# is de-asserted and the device completes its 10 ms startup sequence.