Diodes Incorporated PI6CB18601ZLAIEX

Overview

PI6CB18601 from Diodes Incorporated is a 6-output PCIe Gen1–Gen4 clock buffer with integrated HCSL termination, 1.8V supply, and SMBus-configurable slew rate/amplitude per output. It accepts 100MHz (also 50/125MHz via SMBus) HCSL input, delivers six low-jitter differential outputs (<50ps cycle-to-cycle jitter), and blocks outputs until PLL lock - used in high-speed server motherboard clock distribution.

For engineers reviewing the PI6CB18601 datasheet, PI6CB18601 pinout, PI6CB18601 application, or PI6CB18601 equivalent, key selection criteria include PCIe Gen4-compliant jitter performance, on-chip 50Ω HCSL termination, individual OE# control per output, and 3.3V-tolerant SMBus configuration for multi-frequency support.

Technical Context

The PI6CB18601 implements a proprietary PLL architecture optimized for PCIe timing compliance, supporting three operating modes: low-bandwidth PLL (1.0–2.0 MHz), high-bandwidth PLL (2.0–4.0 MHz), and PLL bypass. Input frequency selection (50/100/125 MHz) is programmable via SMBus register Byte 3 or strapping pins BW_SEL_TRI and SADR_TRI.

Each of the six HCSL outputs features independent enable (OE0#–OE5#), programmable slew rate (two settings), and amplitude control (0.6–0.9 V), all configurable via SMBus or hardware strapping. Differential outputs remain blocked until PLL lock detection completes (~20 ms), ensuring clean startup sequencing in multi-rail systems.

Key Specifications

Pinout & Package

Package: 40-lead 5×5 mm TQFN (exposed pad), RoHS-compliant, halogen-free.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock buffer applications.

Compared with IDT8T49N242A and Si53302-A01AGM, the PI6CB18601 uniquely combines on-chip HCSL termination, SMBus-strappable multi-frequency support, and per-output configurability - making it optimal for space-constrained, multi-protocol PCIe platforms requiring design flexibility and BOM reduction.

Availability

PI6CB18601 is available at Aetrix Electronics and suitable for server motherboard design, PCIe switch card manufacturing, and industrial embedded computing applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.

Supply support for PI6CB18601 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-performance timing, power management, and signal integrity solutions for computing and communications markets.

The PI6CB18601 belongs to Diodes' PCIe-optimized clock buffer product line, designed specifically to reduce system-level timing complexity in high-density, multi-lane PCIe Gen4 platforms while minimizing external component count and layout overhead.

FAQ

What is the function of the PD# pin on the PI6CB18601?

The PD# pin is an active-low CMOS input that controls hardware power-down mode. When pulled low, it disables all outputs and reduces total supply current to ≤0.8 mA. Upon rising edge, the device exits power-down, powers up internal circuitry, and initiates PLL lock sequence (~20 ms). An internal pull-up resistor ensures defined state during power-up.

Can the PI6CB18601 generate 50MHz or 125MHz outputs without changing the input clock?

Yes - the PI6CB18601 supports 50MHz and 125MHz output frequencies while accepting a fixed 100MHz input clock, using its internal PLL with SMBus-programmed frequency select bits (Byte 3, FSEL1/FSEL0). This enables multi-protocol timing from a single crystal source, verified in Diodes' DS40505 Rev 4-2 datasheet Section "Frequency Select Table".

How does the on-chip HCSL termination work, and what is its value?

The PI6CB18601 integrates 50Ω Thevenin-equivalent termination (25Ω series + 25Ω to VDDO) per differential output pair, eliminating need for external 50Ω resistors. This is confirmed in the Block Diagram and "Features" section of DS40505, reducing PCB area by ~24 components and improving signal integrity by minimizing stub effects and impedance discontinuities.

Is the SMBus interface truly 3.3V tolerant, and what happens if driven with 1.8V logic?

Yes - the SMBus inputs (SCLK/SDATA) are specified for 3.3V tolerance (VIH = 2.1V min at VDDSMB = 3.3V) and operate down to 1.7V VDDSMB. Driving with 1.8V logic violates the VIH specification (requires ≥0.75×VDD = 1.35V, but margin is marginal); Diodes recommends using 3.3V SMBus hosts or level-shifting for guaranteed interoperability per Section "SMBus Electrical Characteristics".